Using Emulation to Validate a Cluster Tool Simulation
H. Todd LeBaron and Ruth Ann Hendrickson (Brooks Automation, Inc.)
Getting the most productivity per square foot of clean room space is a common goal for today’s semiconductor fabs. Cluster tool throughput is an important factor in a tool’s productivity index. Maximizing and accurately predicting throughput is a high priority in the cluster tool market. This paper presents a flexible and sufficiently accurate cluster tool simulation model. The simulation model can run as an emulator, using the real-world cluster tool scheduler (CTS), or as a stand-alone simulation model using a rule-based scheduler. The process of validating the stand-alone simulation rule-based scheduler against the actual cluster tool scheduler is discussed. A comparison between the two schedulers is detailed. Finally, the results, benefits, and limitations of the simulation model are presented.
Productivity Modeling of Semiconductor Manufacturing
Mark Pool and Robert Bachrach (Applied Materials, Inc.)
Optimizing a semiconductor wafer fab requires balancing technology and productivity. Recent work on productivity modeling will be described and focus on discrete event simulation models of unitary tool, modules, and whole fab. In addition, some related cost-modeling aspects will be presented. The Applied Materials Turbo Modules Environment is reviewed. Turbo-Modules Unitary Tool Models (UTM) were developed for determining a configured tool's performance, and the Tool Group Models (TGM) were developed for exploring module and fab modeling. Turbo-Modules is based on AutoSimulations, Inc. (ASI) AutoSched AP's open architecture and a customized Graphical User Interface (GUI). The presentation provides a case study performed to analyze the loss of accuracy in a tool group model by modeling unitary tools as black box. Some fab cost modeling will be discussed.
Alternative Loading and Dispatching Policies for
Furnace Operations in Semiconductor Manufacturing: A Comparison by
Elif Akçali and Reha Uzsoy (Purdue University) and David G. Hiscock, Anne L. Moser, and Timothy J. Teyner (Intersil)
In semiconductor manufacturing, furnaces are used for diffusion and deposition operations. A furnace is a batch processing machine, which can simultaneously process a number of lots together as a batch. Whenever a furnace becomes available, scheduling the next batch involves decisions on both which operation to process next (dispatching policy) and how many lots to put into the batch (loading policy). A simulation model of a wafer fabrication facility is used to examine the effects of different loading and dispatching policies for diffusion operations. Results indicate that the loading policy has a significant effect on the average diffusion flow time as well as the overall cycle time of the products, whereas dispatching policy has a less significant effect. We show that the production volume of a product should be considered in setting the minimum number of lots needed to start a batch. We suggest that the diffusion flow time for a low volume product can be reduced by releasing the product in batches or by setting the minimum batch size such that the work-in-process of the product can be moved faster.
Analysis of the Instationary Behavior of a Wafer Fab
during Product Mix Changes
Mathias A. Dümmler (University of Würzburg)
This paper presents a series of experiments that were conducted to investigate in the instationary behavior of a wafer fab after changes in product mix. The experiments were performed using a simulation model of the front end area of an existing semiconductor fab. We observe how short-term increases in wafer starts of a product influence the cycle time and WIP of this product and of the other products. It is examined how the fab recovers from such production surges under different dispatch rules. We also investigate how different lot start mechanisms affect the short term fab performance. More specifically, we observe the effects of changing the mix of the lots started into the fab on a weekly basis. Finally, we compare two alternative ways of releasing lots into the fab: The first way is to distribute lot starts evenly over a given period, e.g. a week, the other way is to start all lots at the beginning of the period.
Cluster Tool Simulation Assists the System
Sarayuth Poolsup (The Model Builders, Inc) and Salil Deshpande (The Model Builders, Inc.)
Designing semiconductor cluster tool systems is a complicated task due to the nature of automatic operations and various configurations of modules and task response priorities of robots. System designers have to synchronize the wafer processing time of each module with robot operation times in order to obtain maximum throughput from the system. A simulation model was developed to reflect the process flows of wafers to and from wafer carriers through various modules in the cluster tool system. The model was first utilized to ascertain the best system configuration of the proposed systems, then utilized to design a cluster tool system that will meet the specific customer requirements.
Partitioning Parallel Simulation of Wireless
Azzedine Boukerche and Alessandro Fabbri (University of North Texas)
In this paper, we present a simulation testbed for wireless and mobile telecommunication systems, a two-stage PCS parallel simulation testbed which makes use of a conservative scheme at Stage 1, and of time warp at Stage 2. While Time warp is considered to be an effective synchronization mechanism in parallel and distributed discrete event simulation (PDES) it is also well known for its unstability due to rollbacks and its devastating effect, i.e., serie of cascading rollbacks, among other factors. Thus, our primary goal in this paper is to study the impact and the importance of partitioning in our PCS model while reducing significantly the number of rollbacks.
Maximizing Delivery Performance in Semiconductor Wafer
Scott J. Mason (Univesity of Arkansas) and John W. Fowler (Arizona State University)
This paper is motivated by the problem of scheduling customer orders (jobs) in a semiconductor fabrication facility (“wafer fab”) to maximize delivery performance when the jobs have non-identical priorities (weights). As each job is typically assigned a weight based on its size, value, and/or requesting customer, a wafer fab’s delivery performance can be evaluated in terms of minimizing the sum of each job’s weighted tardiness. A heuristic has been proposed for obtaining “good” solutions to this complex problem. Using a “real world” wafer fab data model, the heuristic is compared to a number of dispatching rules in terms of how well each method produces job sequences that maximize delivery performance of customer orders. Results suggest that the heuristic consistently produces the best overall schedules, but there is a price to be paid in terms of solution speed.
Simulation Based Cause and Effect Analysis of Cycle
Time Distribution in Semiconductor Backend
Appa Iyer Sivakumar (Nanyang Technological University)
We analyzed the effect of a number of controllable input parameters on cycle time distribution and other output variables in a complex semiconductor backend manufacturing system, using a data driven, discrete event simulation model. A validated model was used as the base case and the effects were quantified against the base model to analyze the relative merits and sensitivity of each of these input variables. Input variables that are analyzed include lot release controls, heuristic scheduling rules, machine up time, setup time, material handling time, product flow, and lot size. We have used actual data from a major semiconductor back-end site for our analysis and showed the impact of lot release scheduling on cycle time distribution.
Scheduling MEMS Manufacturing
Wang Lixin, Francis Tay Eng Hock, and Lee Loo Hay (National University of Singapore)
This paper focuses on the production scheduling in MEMS (Micro-Electro Mechanical System) manufacturing. The whole MEMS production process can be organized into 3 sub-processes, i.e., the wafer front-end process, the wafer cap process and the back-end process. Every wafer processed by the wafer front-end process needs to be bonded with a wafer that is manufactured in the wafer cap process, and then it will be sent to the back-end process. Therefore how to synchronize the release of wafers into the front-end process as well as the wafer cap process becomes an important topic. An ineffective coordination will create long cycle time and large WIP (work-in-process). In this paper, four synchronization rules are developed and they are evaluated together with two release rules and five dispatching rules. The performance measures considered are cycle time, throughput rate and WIP. A visual interactive simulation model is constructed to imitate the production line. The simulation results indicate that synchronization rules, release rules, and dispatching rules, have significant impacts on the performance of MEMS manufacturing and the best policy combination is Littlesyn-CONWIP-SRPT.
Why do Simple Wafer Fab Models Fail in Certain
Oliver Rose (University of Würzburg)
Previous work has proved that simple simulation models are sufficient for analyzing the behavior of complex wafer fabs in certain scenarios. In this paper, we give an example where the simple model fails to accurately predict cycle times and WIP levels of the complex model. To determine the reason for this behavior, we analyze the correlation properties of a MIMAC full fab model and the corresponding simple one. It turns out that the simple model is not capable of capturing the correlations in an adequate way because there is lot overtaking (passing) in the simple model while almost no overtaking can be found in the complex counterpart.
Understanding the Impact of Equipment and Process
Changes with a Heterogeneous Semiconductor Manufacturing Simulation
Jeffrey W. Herrmann, Brian F. Conaghan, Laurent Henn-Lecordier, Praveen Mellacheruvu, Manh-Quan Nguyen, Gary W. Rubloff, and Rock Z. Shi (University of Maryland)
Simulation models are useful to predict and understand the impact of changes to a manufacturing system. Typical factory simulation models include the parts being manufactured in the factory and the people and resources processing and handling the parts. However, these models do not include equipment or process details, which can affect operational performance such as cycle time and inventory. Separate models are used to evaluate processes and equipment. Thus, it is difficult to evaluate the operational impact of equipment or process changes. However, this information could help factory managers and manufacturing process engineers make better decisions when changing processes or selecting equipment configurations. This paper describes a heterogeneous simulation environment for understanding how equipment and process changes affect the performance of a wafer fabrication facility. This integrated tool incorporates response surface models that describe process behavior, operational and optimization models of equipment behavior, and a discrete-event simulation model of factory operations. Thus, the tool can measure how process changes and equipment configuration changes change the system performance. We have applied this tool to a specific wafer fab problem.
Evaluation of the Effectiveness of Group
Screening Methods as Compared to No Group Screening
Dima Nazzal (Cirent Semiconductor) and Mansooreh Mollaghasemi and Linda C. Malone (Univesity of Central Florida)
The focus of the paper is on the comparison of results obtained using group screening versus not using group screening in an experimental design methodology applied to a semiconductor manufacturing simulation model. The experiments were performed on the cycle time for the main product in the fab, which takes about 250 steps before completion. High utilization and large queue sizes were the basis for determining the five most critical workstations in the fab. Three parameters for each workstation were set as factors for investigation plus another more general important factor making a total of 16 input factors. A 2-stage group-screening experiment and a 2k-p factional factorial were performed to identify the significant factors affecting the cycle time for the product. The results showed that the two methods could be very similar or very different depending on the choice of significance level for group screening, particularly at the early stages of eliminating group-factors.
Integrating Dynamic Fab Capacity and Automation Models
for 300mm Semiconductor Manufacturing
Chad D. DeJong and Seth A. Fischbein (Intel Corporation)
Semiconductor fabrication facilities continue to expand in complexity and volume. As a result, integrated models are required to determine high level impacts to key success indicators. Intel uses dynamic discrete-event simulation fab capacity and automation models. In order to gain insight into how the components of a factory impact performance metrics, Intel uses an integrated modeling approach. This paper discusses the methodology for building and integrating both models, and the results from using this method. Both the fab capacity and automation models have several input parameters that are required to drive the simulation. In addition, each model produces output parameters, some of which are used as inputs to the other model. An iterative feedback technique eventually results in a convergence on the appropriate data to feed the fab capacity model, which then allows the analysis of the impact of automation on 300mm wafer semiconductor manufacturing. Both the fab capacity and automation dynamic discrete-event simulation models are used to determine each system’s impact to the other, and the final predicted factory performance. This approach provides the capability to use the models in stand-alone, and also via a model communication. Intel continues to search for new applications for these merged models to answer strategic operational questions.
A Simulation-based Cost Modeling Methodology for
Evaluation of Interbay Material Handling in a Semiconductor Wafer
Shari Murray, Gerald T. Mackulak, and John W. Fowler (Arizona State University) and Theron Colvin (IM&AGE Factory Services)
In the next generation of semiconductor wafer fabrication facilities, decisions concerning material handling systems will be a major factor in initial facility cost, operational cost, production cycle times, and possibly product yield percentages. The wafers will increase in diameter to 300 mm and a new front opening unified pod (FOUP) has been designed to carry them, both increasing the weight of a production lot. This increase requires substantial automation for ergonomic and quality reasons. As a result, semiconductor manufacturers are asking, “What level of automation is financially justifiable?” Automation suppliers have stated that automation saves money, but have as yet not produced a sufficiently detailed financial analysis proving their premise. In this paper, both a fully automated and a manual material handling system are simulated and compared in a thorough cost analysis. Sensitivity analysis is performed on inflation rate, interest rate, die price, wafer start rate, and yield percentage to validate the results of the analyses.
Simulation Based Decision Support for Future 300mm
Automated Material Handling
Mathias Schulz and Timothy D. Stanley (SEMICONDUCTOR300), Bernhard Renelt (Infineon Technologies Dresden) and Roland Sturm and Oliver Schwertschlager (Fraunhofer Institute Manufacturing Engineering and Automation (FhG-IPA))
Integrated factory models of semiconductor fabrication facilities allow conclusions to be drawn on the impact of a given Automated Material Handling System (AMHS) and interactions between material flow and factory performance. A generic model of a 300mm fab has been built to support decisions to be made in terms of dimensioning of the potential AMHS solutions.