WSC 2001 Final Abstracts

Semiconductor Manufacturing Track

Monday 10:30:00 AM 12:00:00 PM
Bottleneck Equipment Management

Chair: Oliver Rose (University of Würzburg)

Simulating Test Program Methods in Semiconductor Assembly Test Factories
Chad D. DeJong (Intel Corporation)

Significant opportunities for improvement in semiconductor manufacturing reside in the Test areas. These Test areas can often be the system constraint, due to complex testing policies, bin-to-order mapping, and cost. A very difficult problem is to determine the best methods for assigning test programs for lots on these test equipment. To answer these problems, Intel has produced dynamic discrete event simulation models that consider multiple wafer types, multiple end products, multiple test program methods, and binning policies of end products according to the tested performance of the die. This model does not require modeling specific manufacturing equipment and operator activities, only detailed logic of test program and binning policies. The quantitative output data from this model provides the relative decision support necessary to determine what methods work best for Intel, given other costs and business drivers.

How “Overstaffing” at Bottleneck Machines Can Unleash Extra Capacity
Robert C. Kotcher (Headway Technologies, Inc.)

Using simulation, Headway Technologies predicted that increasing staffing among a group of already lightly loaded machine operators-—"overstaffing"—-would significantly improve throughput of its factory. This was counterintuitive since the operators already had significant idle time. Yet time studies confirmed that bottleneck equipment for which these operators were responsible was spending over 22% of its uptime idle solely due to lack of an operator. Analysis showed how this could be so: production equipment has a frequent and unpredictable need for operators, yet the operators must spend time away from the equipment tending to other demands of their jobs. A method of estimating the cost of this operator-induced throughput loss is described. The result shows how extremely profitable the hiring of extra operators is in such situations. A means of estimating the most profitable level of staffing is also described, along with several alternative solutions for reducing operator absences.

Simulation-Based Solution of Load-Balancing Problems in the Photolithography Area of a Semiconductor Wafer Fabrication Facility
Lars Mönch (Technical University of Ilmenau) and Matthias Prause and Volker Schmalfuss (X-FAB Semiconductor Foundries AG)

In this paper we present the results of a simulation study for the solution of load-balancing problems in a semiconductor wafer fabrication facility. In the bottleneck area of photolithography the steppers form several different subgroups. These subgroups differ, for example, in the size of the masks that have to be used for processing lots on the steppers of a single group. During lot release it is necessary to distribute the lots over the different stepper groups in such a way that global targets like cycle time minimization, the maximization of the number of finished lots and due date performance are inside a certain range. We present a simulation model of a wafer fab that models the photolithography area in a detailed manner. By means of this simulation model it is possible to decide at release time on which stepper subgroup processing of the lots of a certain product is favorable.

Monday 1:30:00 PM 3:00:00 PM
Cycle Time versus Throughput Analysis

Chair: DeJong Chad (Intel)

An Overall Framework for Generating Simulation-Based Cycle Time-Throughput Curves
Sungmin Park (Korea Gas Corporation) and Gerald T. Mackulak and John W. Fowler (Arizona State University)

A simulation-based cycle time-throughput curve requires a large amount of simulation output data, and an experimentation framework is needed to enhance the precision and accuracy of a simulation-based cycle time-throughput curve. In this research, approaches and solutions are presented on three prime issues: 1) the establishment of the simulation sampling strategies; 2) the determination of the simulation sequences; and 3) the determination of the length of a simulation run. First, strategic simulation sampling guidelines are proposed as to how to use a fixed amount of samples when trying to generate a precise and accurate cycle time-throughput curve for complex systems. Second, in order to provide good references for the sequential experiments to generate precise simulation-based cycle time-throughput curves, a set of discrete design points is ranked sequentially. Third, a sequential stopping rule is developed to determine the length of a simulation run based on a time series forecasting procedure.

Sizing a Pilot Production Line Using Simulation
Peng Qu, Geoffrey E. Skinner, and Scott J. Mason (University of Arkansas)

The semiconductor industry is rapidly expanding worldwide. With the continuing advancement of technology, companies are continually striving to develop and maintain cutting edge products to stay “ahead of the curve.” As a result, old and new companies alike often have the need to develop pilot production lines to test new engineering and processing ideas. We present a case study example of how simulation can be used to establish the initial tooling and operator requirements for pilot production lines, as well as to estimate the fixed and recurring costs associated with the line.

Critical Tools Identification and Characteristics Curves Construction in a Wafer Fabrication Facility
Dima Nazzal and Mansooreh Mollaghasemi (University of Central Florida)

The purpose of this research was to identify the factors in a wafer fabrication facility that significantly affect the cycle times of two main technologies that are currently in process and in demand for the next few years. Moreover, the goal was to construct the characteristics curves that would provide information about the different capabilities of a wafer fabrication facility for several improvement scenarios. A valid simulation model of the whole production line of the fabrication facility was built. The input factors in the fab that significantly affect cycle time, were identified through factor screening experiments. Based on these factors, several scenarios involving addition of tools, were identified and the characteristics curves were constructed for each scenario. These characteristics curves were used to relate cycle time to production volume capacities.

Monday 3:30:00 PM 5:00:00 PM
Scheduling and Dispatching

Chair: Russell Barton (Penn State University)

Scheduling Batch Processing Machines in Complex Job Shops
Kasin Oey and Scott J. Mason (University of Arkansas)

This paper considers a complex job shop problem with reentrant flow and batch processing machines. A modified shifting bottleneck heuristic (MSB) is considered for generating machine schedules to minimize the total weighted tardiness. We observe that the MSB could produce infeasible schedules where cyclic schedules are found. A cycle elimination procedure is proposed to remove the possibility of the MSB generating cyclic schedules in the solution.

Scheduling Setup Changes at Bottleneck Facilities in Semiconductor Manufacturing
Zaid Duwayri (i2 Technologies) and Mansooreh Mollaghasemi and Dima Nazzal (University of Central Florida)

In this paper, a scheduling heuristic was developed to aid the operators in semiconductor fabs in choosing what type of lots to process next on bottleneck facilities, and whether to change machine setup in order to reduce cycle time. The scheduling heuristic aims at balancing workload levels for implanters processing lots at different stages of the wafer production lifecycle. This is accomplished by processing lots that contribute most to increasing inventory levels at the bottleneck facility. A whole production line simulation model was used to evaluate the performance of the scheduling heuristic and to compare it against several commonly used scheduling heuristics with respect to mean cycle time, work in process (WIP), and standard deviation of cycle time. Simulation results showed that the heuristic performed better than all other rules in terms of mean cycle time and WIP in all cases, and better in terms of standard deviation of cycle time for most cases tested.

Dispatching Heuristic for Wafer Fabrication
Loo Hay Lee, Loon Ching Tang, and Soon Chee Chan (National University of Singapore)

As the semiconductor industry moves into the next millennium, companies increasingly will be faced with production obstacles that impede their ability to remain competitive. Effective equipment and line management planning will increasingly be required to maximize profitability while maintaining the flexibility to keep pace with rapidly changing manufacturing environment. In this paper, the authors present a two-bottleneck machines center model for wafer operations analysis. A new dispatching rule Balance Work Content, BWC, is introduced. This is a selective dispatching rule whereby it attempts to maximize the utilization of bottleneck machine. A systematic approach to assessing the impact of BWC is presented. Extensive simulation runs on both the deterministic and stochastic models developed shows its supremacy over conventional approaches of FIFO and SPT.

Tuesday 8:30:00 AM 10:00:00 AM
Modeling Methodology

Chair: Scott Mason (University of Arkansas)

The Shortest Processing Time First (SPTF) Dispatch Rule and Some Variants in Semiconductor Manufacturing
Oliver Rose (University of Würzburg)

Looking for appropriate dispatch rules for semiconductor fabrication facilities (wafer fabs), practitioners often intend to use the Shortest Processing Time First (SPTF) rule because it is said to reduce cycle times. In our study, we show, however, that this positive effect on cycle times can be achieved in single machine systems but not necessarily in complete wafer fabs. In addition, we discuss variants of the SPTF rule.

Implementation of Response Surface Methodology Using Variance Reduction Techniques in Semiconductor Manufacturing
Charles D. McAllister, Bertan Altuntas, and Matthew Frank (The Pennsylvania State University) and Juergen Potoradi (Infineon Technologies)

Semiconductor manufacturing is generally considered a cyclic industry. As such, individual producers able to react quickly and appropriately to market conditions will have a competitive advantage. Manufacturers who maintain low work in process inventory, ensure that specialized equipment is in good repair, and produce quality products at least possible cost will have the best opportunities to effectively compete and excel in these challenging venues. To support this nimble business model, our current efforts are directed toward creating efficient, accurate metamodels of the impact of maintenance policies on production efficiency. These validated polynomial approximations facilitate rapid exploration of the design region, compared with the original simulation models. The experiment design used for metamodel construction employed variance reduction techniques. When compared to a similar experiment design using independent streams, the variance reduction approach provided a decrease in standard error of the regression coefficients and smaller average error when validated against the simulation response.

Graphical Methods for Robust Design of a Semiconductor Burn-In Process
Scott L. Rosen, Chad A. Geist, Daniel A. Finke, Jyotirmaya Nanda, and Russell R. Barton (The Pennsylvania State University)

Discrete-event simulation is a common tool for the analysis of semiconductor manufacturing systems. With the aid of a simulation model, and in conjunction with sensitivity analysis and metamodeling techniques, robust design can be performed to optimize a system. Robust design problems often include integer decision variables. This paper shows a graphical approach to robust design that is effective in the presence of discrete or qualitative variables. The graphical robust design methodology was applied to a backend semiconductor manufacturing process. Changes in specific resource capacities and product mix were examined to determine their effect on the level and variance of cycle time and work in process.

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