WSC 2002

WSC 2002 Final Abstracts

Semiconductor Manufacturing Track

Monday 10:30:00 AM 12:00:00 PM
Wafer Fabrication

Chair: Chad DeJong (Intel Corporation)

Effects of Metrology Load Port Buffering in Automated 300mm Factories
Robert Wright, Marlin Shopbell, Kristin Rust, and Silpa Sigireddy (International SEMATECH)

This paper describes a simulation study characterizing the advantages and disadvantages of implementing multiple load ports on metrology equipment in a semiconductor factory. Three methods of automated material handling (AMH) for 300 mm wafer carriers in four separate models were analyzed: Through Stocker, Point-to-Point, and Conveyor (slow and fast velocity). Parameters measured include idle times of metrology equipment as number of load ports change and the effects on bottleneck equipment, work in process (WIP), queue lengths, transport times, delays waiting for transportation to begin, and the effect on stocker utilization by bay.

300mm Wafer Fabrication Line Simulation Model
Sameer T. Shikalgar, David Fronckowiak, and Edward A. MacNair (IBM)

The importance of semiconductor wafer fabrication has been increasing steadily over the past decade. Wafer fabrication is the most technologically complex and capital intensive phase in semiconductor manufacturing. It involves the processing of wafers of silicon in order to build up layers and patterns of metal and wafer material. Many operations have to be performed in a clean room environment to prevent particulate contamination of wafers. Also, since the machines on which the wafers are processed are expensive, service contention is an important concern. All these factors underline the importance of seeking policies to design and operate them efficiently. We describe a simulation model of a planned 300mm wafer fabrication line that we are using to make strategic decisions related to the factory.

Realizing 300mm Fab Productivity Improvements through Integrated Metrology
K. J. Stanley and Timothy D. Stanley (International SEMATECH) and Jose' Maia (Technical University of Lisbon)

The operational cost of 300mm wafer production is significantly greater than that of 200mm fabs. Real-time monitoring of product can save time and money through reduced scrap and decreased cycle time. Current process monitoring generally incorporates stand-alone metrology, which is time consuming and requires excessive wafer handling by production operators. The benefits of integrated metrology are measured by considering the impact of metrology on a semi-conductor fab through simulation modeling. Since the process and metrology steps are in series, overall process throughput depends on metrology methods. Furthermore, the measurements impact WIP (Work In Process) inventory. WIP is at risk if the process drifts. Send-ahead samples reduce WIP risk but also reduce process throughput and tool utilization. Integrated metrology minimizes risk but may decrease throughput rate. This paper explores the operational benefits of integrated metrology strategies versus stand-alone metrology via simulation modeling.

Monday 1:30:00 PM 3:00:00 PM
Material Handling

Chair: Oliver Rose (University de Wuerzburg)

Operational Modeling and Simulation of an Inter-Bay AMHS in Semiconductor Wafer Fabrication
Jesus Jimenez, Bosun Kim, John Fowler, Gerald Mackulak, and You In Choung (Arizona State University) and Dong-Jin Kim (Samsung Electronics)

This paper studies the operational logic in an inter-bay automated material handling system (AMHS) in semiconductor wafer fabrication. This system consists of stockers located in a two-floor layout. Automated moving devices transfer lots between stockers within the same floor (intra-floor lot transfer) or between different floors (inter-floor lot transfer). Intra-floor lot-transferring transports use a two-rail one-directional system, whereas inter-floor lot-transferring transports use lifters. The decision problem consists of selecting rails and lifters that minimize average lot-delivery time. Several operation rules to deliver lots from source stocker to destination stocker are proposed and their performance is evaluated by discrete event simulation.

Data-Based Node Penalties in a Path-Finding Algorithm in an Automated Material Handling System
Miki Fukunari, Srinivas Rajanna , Robert J. Gaskins, and Mary Ellen Sparrow (Brooks-PRI Automation, Inc.)

Increasing factory throughput is a critical issue in the semiconductor industry, and a quick transition of material to the next location in the automation system plays a significant role in increasing throughput. A dynamic path-finding algorithm for a vehicle-based automated material handling system (AMHS) is discussed in this paper. The dynamic path-finding algorithm uses distance between nodes, node penalties, and the number of vehicles queued to calculate the total cost of a path. This paper introduces the use of historical data from the AMHS and discusses how to effectively utilize such data in critical situations to improve overall AMHS performance.

Simulating the Transport and Scheduling of Priority Lots in Semiconductor Factories
Chad D. DeJong and Scott P. Wu (Intel Corp.)

As the high technology product market becomes more dynamic and competitive, chip manufacturers need to bring products to customers in short periods of time. As a result, semiconductor fabrication plants regularly contain lots with priority status. These lots have several unique characteristics compared to other production lots, both in terms of lot transport and scheduling on tools. These lots consume tool capacity that may impact the factory output rate. Priority lots also have specific policies for transport. The impact of these priority lots on other lots in the fab is not easily quantified, as many factors are involved. Dynamic factory and AMHS simulation models are capable of capturing the variability of a factory, and the interactions of critical constraints that prevent predictable manufacturing. This paper presents a breakthrough modeling approach to study the behaviors of priority lots, and to quantify their impact to manufacturing.

Monday 3:30:00 PM 5:00:00 PM
Scheduling and Dispatching

Chair: Russell Barton (The Pennsylvania State University)

A Simulation Study on Release, Synchronization, and Dispatching in MEMS Fabrication
Lixin Wang (Gintic Institute of Manufacturing Technology) and Loo Hay Lee (National University of Singapore)

MEMS (microelectromechanical system) fabrication can be organized as three sub-processes, that is, the front-end process, the wafer cap process, and the back-end process. The coordination between the releases of raw wafers to the two parallel sub-processes, the front-end process, and the wafer cap process, is always an important issue. Previous research work has developed synchronization rules to create effective coordination. In this paper, new synchronization rules and dispatching rules are developed and they are evaluated with more release rules. From this much more extensive simulation experiment, it is found that there are significant two-factor and three-factor interactions among these three types of rules and we have to consider them all together in order to achieve the best performance for MEMS fabrication system. Moreover, the complicated relationship between the performances (cycle time and total work-in-process) is also indicated.

Some Issues of the Critical Ratio Dispatch Rule in Semiconductor Manufacturing
Oliver Rose (University of Würzburg)

In this paper, we examine the cycle time and on-time delivery performance of a semiconductor wafer fabrication facility (wafer fab) under critical ratio (CR) dispatch regime. It turns out that determining appropriate due dates for this rule is a critical task. We provide a detailed analysis of the wafer fab behavior for a large range of due date values. From the results of the experiments we develop a heuristic for conservative due date estimates.

A Finite-Capacity Beam-Search-Algorithm for Production Scheduling in Semiconductor Manufacturing
Ilka Habenicht (Technical University of Ilmenau) and Lars Mönch (Tecnical University of Ilmenau)

In this paper we describe a finite-capacity algorithm that can be used for production scheduling in a semiconductor wafer fabrication facility (wafer fab). The algorithm is a beam-search-type algorithm. We describe the basic features of the algorithm. The implementation of the algorithm is based on the ILOG-Solver libraries. We describe the simulation environment, which is used to evaluate the performance of the proposed algorithm. We show some results from computational experiments with the algorithm and the simulation test-bed described.

Tuesday 8:30:00 AM 10:00:00 AM
Modeling Methodology

Chair: Dave Miller (IBM)

New Approaches for Simulation of Wafer Fabrication: The Use of Control Variates and Calibration Metrics
Chanettre Rasmidatta, Shari Murray, John W. Fowler, and Gerald T. Mackulak (Arizona State University)

Simulation-based wafer fabrication optimization models require extensive computational time to obtain accurate estimates of output parameters. This research seeks to develop goal-driven optimization methodologies for a variety of semiconductor manufacturing problems using appropriate combinations of "resource-driven" (R-D), "job-driven" (J-D), and Mixed (combination of R-D and J-D) models to reduce simulation run times. The initial phase of this research investigates two issues: a) the use of the R-D simu-lation control variates for the J-D simulation and b) development of metrics that calibrate the output from the R-D and J-D modeling paradigms. The use of the R-D model as a control variate is proposed to reduce the variance of J-D model output. Second, in order to use the R-D model output to predict the J-D model output, calibration metrics for the R-D and J-D modeling approaches were developed. Initial developments were tested using an M/M/1 queuing system and an M/D/1 queuing system.

Simulation based Cause and Effect Analysis of Cycle Time and WIP in Semiconductor Wafer Fabrication
Chao Qi, Tuck Keat Tang, and Appa Iyer Sivakumar (Nanyang Technological University)

Semiconductor wafer fabrication is perhaps one of the most complex manufacturing processes found today. In this paper, we construct a simulation model of part of a wafer fab using ProModel® software and analyze the effect of different input variables on selected parameters, such as cycle time, WIP level and equipment utilization rates. These input variables include arrival distribution, batch size, downtime pattern and lot release control. SEMATECH DATASET which has the original actual wafer fab data is used for our analysis.

Using Simulation to Understand Capacity Constraints and Improve Efficiency on Process Tools
Manuel Aybar and Kishore Potti (Texas Instruments) and Todd LeBaron (Brooks-PRI Automation)

Finding hidden capacity and maximizing cluster tool throughput is a common goal for today’s semiconductor manufacturers. This presentation will discuss a flexible and accurate simulation program capable of modeling a wide range of semiconductor process tools. The simulation program provides visibility and understanding into the internal dependencies and interactions of each process tool. This information provides a solid base from which sound decisions can be made. Simulation results from two case studies will be presented. The real-world capacity improvements, cycle time reductions, and cost savings will be presented.

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