WSC 2003

WSC 2003 Final Abstracts

Semiconductor Manufacturing Track

Monday 10:30:00 AM 12:00:00 PM
Factory Scheduling and Dispatching

Chair: Oliver Rose (University of Würzburg)

Constant Time Interval Production Planning with Application to WIP Control in Semiconductor Fabrication
Kazuo Miyashita (Natl. Inst. of Advanced Industrial Science & Technology) and Kazuyuki Senoh, Hiroyuki Ozaki, and Hirofumi Matsuo (Institute of Policy & Planning Sciences)

We develop a constant time interval production planning and control methodology, called CONSTIN, and its associated simulation system for a large-scale and unstable semiconductor manufacturing process. CONSTIN moves work-in-process inventories (WIP) between processes only at a constant time interval, and consequently maintains a desirable level of WIP. Our theoretical and experimental analysis shows a clear relationship between WIP levels and the time interval in CONSTIN. Computational experiments with realistic wafer fabrication process data demonstrate that CONSTIN is comparable in simulation accuracy to a popular event-driven simulator and can run much faster. Additional experiments also manifest that, with appropriate control rules, CONSTIN can restore the desired levels of WIP from extreme deviations and maintain them. Therefore, we conclude that CONSTIN is a promising methodology of production planning and WIP control for the semiconductor manufacturing process.

Simulation-Based Assessment of Batching Heuristics in Semiconductor Manufacturing
Lars Mönch and Ilka Habenicht (Technical University of Ilmenau)

In this paper, we investigate the performance of different dispatching and scheduling heuristics for batching tools in a semiconductor wafer fabrication facility (wafer fab) by means of discrete event simulation. Because the processing times of lots on batching tools are quite large compared to those of other processes, careful batching decisions may have a great impact on the performance of the entire wafer fab. In a first step, we investigate the performance of certain modifications of the Apparent Tardiness Cost (ATC) dispatching rule that do not take into account future lot arrivals. In a second step, we extend this approach by considering future lot arrivals. In a last step, we combine a genetic algorithm for assignment of the batches to parallel machines with the ATC rule, which takes future lot arrivals into account. We present results of simulation experiments with the different heuristics.

Accelerating Products under Due-Date Oriented Dispatching Rules in Semiconductor Manufacturing
Oliver Rose (University of Würzburg)

In semiconductor manufacturing facilities, there is often the need to speed up certain product types. This is usually done by either assigning higher priorities or by reducing due dates. In this paper, we study the effects of accelerating one product type by a tighter due date on the on-time delivery performance of the other products manufactured. It turns out that the results depend on the considered factory, its load, and the accelerated product. As a consequence, it will be hard for production planners to find simple rules of thumb for the effects of accelerating products. In general, detailed simulation experiments will be required.

Monday 1:30:00 PM 3:00:00 PM
Automated Material Handling Systems

Chair: David Miller (IBM Microelectronics)

A Simulation-Based Design Framework for Automated Material Handling Systems in 300mm Fabrication Facilities
Dima Nazzal and Douglas A. Bodner (Georgia Institute of Technology)

This paper describes a methodology to tackle the problem of designing Automated Material Handling Systems (AMHS) for 300mm wafer fabrication facilities. The proposed framework divides the design process into two levels: architectural and elaborative. Prior to the design, fab data are preprocessed using simulation of manufacturing operations. The output data and fab requirements data are then profiled to aid in design decision making at the architectural level. Once architectural design decisions are made, lower-level design decisions are made and analyzed using a simulation model that incorporates the AMHS. Due to the potential number of alternatives and time constraints on the design process, we are exploring rapid model generation methods. In this paper, we describe our progress to date in creating this methodology.

Automated Reticle Handling: A Comparison of Distributed and Centralized Reticle Storage and Transport
Anne M. Murray and David J. Miller (IBM Microelectronics)

The implementation of Automated Material Handling Systems (AMHS) in 300mm semiconductor facilities provides the opportunity to realize significant benefits in fabricator productivity and performance. The leverage associated with automated reticle delivery to photolithography process tools may be less apparent than a fab-wide AMHS. However, a high product mix environment requires the tracking, storage and transportation of thousands of reticles to successfully process wafers on photolithography tools. The failure to deliver reticles in an accurate and timely manner will negate many of the competitive advantages associated with automated wafer handling. Implementing an automated reticle management system (ARMS) requires an evolution from traditional reticle storage and management methodologies. In this paper, we review the application of simulation analysis to explore centralized versus distributed reticle storage and handling alternatives for an overall ARMS strategy.

An Approach to Robust Layout Planning of AMHS
Roland Sturm, Joachim Seidelmann, Johann Dorner, and Kevin Reddig (Fraunhofer IPA)

The simulation-based layout planning of automated material handling systems (AMHS) for microelectronics and semiconductor manufacturing demands adequate simulation models. An approach for measuring and quantifying the AMHS layout performance of alternative planning variants is required. Fraunhofer IPA has developed simulation methods and a three level approach for calculation of AMHS performance metrics. This approach is very efficient when comparing alternative planning variants, although the difference in the configuration change is very small. The paper outlines the planning approach for two typical AMHS designs used for interbay transportation in 200mm wafer fabs. The models used are generic and can be adapted easily to different AMHS solutions.

Monday 3:30:00 PM 5:00:00 PM
Factory Capacity and Throughput Planning

Chair: Juergen Potoradi (Infineon Technologies)

Conceptualization, Design and Implementation of a Static Capacity Model
Orkun Ozturk, Melissa Boom Coburn, and Steve Kitterman (Seagate Technology)

This paper describes the methodology used for development of a static capacity model. It is a well-known fact that no matter how sophisticated the dynamic models are, there is always a need for the simple spreadsheet model. The spreadsheet model helps one carry out simple and fast analyses whenever they are needed. At the Seagate Technology’s Recording Head Operations Wafer Manufacturing facility (Bloomington, MN) industrial engineers who worked on capacity planning devised their own versions of static spreadsheet models over the years. As useful as these individual models were, being highly custom-tailored and decentralized made them hard to cross-use and manage. To overcome this problem, the IE department designed and implemented a centralized spreadsheet based static capacity model with features that allow industrial engineers create model outputs the way they want.

Indirect Estimation of Cycle Time Quantiles from Discrete Event Simulation Models Using the Cornish-Fisher Expansion
Jennifer E. McNeill, Gerald T. Mackulak, and John W. Fowler (Arizona State University)

This paper introduces a new technique for estimating cycle time percentiles from discrete event simulation models run at a single traffic intensity. The Cornish-Fisher expansion is used as a vehicle for this approximation, and it is shown that for an M/M/1 system and a full factory simulation model, the technique provides accurate results with low variability for the most commonly estimated percentiles without requiring unreasonable sample sizes. Additionally, the technique provides the advantages of being easy to implement and providing multiple cycle time percentiles from a single set of simulation runs.

Discrete-Event Simulation Using SystemC: Interactive Semiconductor Factory Modeling with FabSim
Holger Vogt (Fraunhofer IMS)

Semiconductor fabrication factories are large enterprises with many toolsets, each having multiple production machines. The process flow is highly reentrant, therefore modeling is best done by discrete-event simulation. To describe such a fab, the author has developed a new discrete event simulator called FabSim. It is written in C++. As the simulation engine it uses SystemC, a C++ class library originally developed for modeling “Systems on a Chip”. The factory with its machines and lots traveling and in process is mapped onto SystemC like a hardware description during RTL (register transfer) modeling. The resulting simulator is compact, fast and efficient. In a special configuration as a MS Windows dynamic link library, the simulator is fully interactive. At any time you may define a stop in the simulation flow, retrieve the state of the whole system, change parameters, add lots, or even enter a new state and continue with the simulation.

Tuesday 8:30:00 AM 10:00:00 AM
Process Equipment Modeling

Chair: Robert Wright (SemaTech)

Making Optimal Design Decisions for Next Generation Dispensing Tools
Brian P. Prescott (Cookson Electronics Equipment) and Todd LeBaron (Brooks Automation Inc.)

The competitive environment faced by semiconductor equipment suppliers leaves no room for error when design-ing next generation tools. In addition, time to market, footprint, and equipment capabilities are all key to a successful product. At Cookson Electronics Equipment, tool designers used simulation to answer some difficult design questions, improve time to market, and lower development costs. This paper explains how simulation was used in designing the new High Volume Batch (HVB) dispensing platform. It also discusses the flexible simulation model and simulation results for various prototype equipment designs.

Application of Cluster Tool Modeling to a 300 mm Fab Simulation
Sameer T. Shikalgar and David Fronckowiak (IBM) and Edward A. MacNair (IBM T.J. Watson Research Center)

300 mm semiconductor wafer fabrication facilities, like conventional semiconductor fabs, contain many different types of tools. In this paper we discuss a realistic way of representing cluster tools in a simulation model of the entire line. A more realistic representation of cluster tools results in greater accuracy in the output of the simulation model.

Resident-Entity based Simulation of Batch Chamber Tools in 300mm Semiconductor Manufacturing
Nirmal Govind (The Pennsylvania State University) and David Fronckowiak (IBM Microelectronics)

This paper describes a resident-entity based pilot simulation study of a class of tools used in 300mm semiconductor manufacturing known as the wets tools or the wet benches. These are batch chamber tools - they have several chambers or tanks, each of which can accommodate a batch of wafers, usually more than one lot size. We develop a simulation model for the wets processing area that is based on the resident-entity paradigm, but makes use of transient-entity-type modeling when more information needs to be tracked. Resident-entity models tend to be much faster than transient-entity simulation models that are common in semiconductor manufacturing. The model developed captures most of the internal workings of a wets tool and at the same time, models different types of tools. We used the model to evaluate the effects of scheduling policies and batching parameters on the performance of the wets process area.

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