WSC 2004

WSC 2004 Final Abstracts

Semiconductor Manufacturing Track

Tuesday 1:30:00 PM 3:00:00 PM
Distributed Simulation of Semiconductor Manufacturing

Chair: Lars Moench (Technical University of Ilmenau)

Distributed simulation promises a range of benefits and opportunities, especially for modeling large-scale complex systems, such as wafer fabs. However, as with many promising technologies, the devil is in the details. This paper describes some experiences in distributing a high-fidelity, full fab simulation model with federates implemented in Java representing manufacturing processes, automated material handling systems, and control systems. Some informal comparisons with AutoMod/ASAP are included.

Analysis of a Borderless Fab Scenario in a Distributed Simulation Testbed
Peter Lendermann, Boon Ping Gan, and Yoon Loong Loh (Singapore Institute of Manufacturing Technology), Hiap Keong Tan and Sip Khean Lieu (Chartered Semiconductor Manufacturing, Ltd.), John W. Fowler (Arizona State University) and Leon F. McGinnis (Georgia Institute of Technology)

Distributed simulation based on the High Level Architec-ture standard is adopted to realize the simulation of a bor-derless fab that involves two wafer fabs located in close proximity. The two fabs pool together their resources for capacity sharing. To demonstrate the benefits of this con-cept, experiments were conducted to measure the cycle time changes resulting from introduction of an additional product into either one of the fabs. In the case without cross fab material flow, the capacity of each fab alone is not sufficient to handle the increasing release rate of the new product as bottleneck machines surface. However, for the cross fab case where the front-end of the new product’s process is done in the first fab, while the back-end in the second, it is possible to avoid the bottleneck situation. As a result, the two fabs are able to increase their aggregated capacity without investing in new equipment.

Analysis of a Customer Demand Driven Semiconductor Supply Chain in a Distributed Simulation Test Bed
Chin Soon Chong, Peter Lendermann, and Boon Ping Gan (Singapore Institute of Manufacturing Technology) and Brett Marc Duarte, John W. Fowler, and Thomas E. Callarman (Arizona State University)

Effective supply chain management (SCM) enables organizations to be more competitive in the current world of global manufacturing by reducing costs and improving the quality of customer service. Simulation can assist in moving towards these goals by evaluating the feasibility of alternative policies for managing a supply chain. However, simulation of multiple factories within the supply chain, with a high level of granularity in particular, can be very complex and computationally intensive. In this paper, we describe how a distributed simulation test bed enabling very detailed supply chain simulation can be used to study a customer-demand driven semiconductor supply chain.

Distributing a Large-Scale, Complex Fab Simulation Using HLA and Java: Issues and Lessons
Leon F. McGinnis (Georgia Institute of Technology)

Tuesday 3:30:00 PM 5:00:00 PM
Semiconductor Equipment Modeling

Chair: Michael Kuhl (Rochester Institute of Technology)

Modeling Tool Failures in Semiconductor Fab Simulation
Oliver Rose (University of Würzburg)

In this research, we investigate how well Weibull, Gamma, and special bimodal distribution are suited as an alternative to the exponential distribution approach in the stochastic modeling of machine downtimes and times between failures. We also discuss the question whether sampling shop-floor data should not only include first order statistics, but also measures that allow to monitor and model the variability of the equipment and processes and even the correct distribu-tion of the data.

An Event Graph Based Simulation and Scheduling Analysis of Multi-Cluster Tools
Shengwei Ding (University of California at Berkeley) and Jingang Yi (Lam Research Corporation)

Simulation methods are extensively used in modeling complex scheduling problems. However, traditional layout of simulation models can become complicated when they are used to find optimal scheduling in complex systems such as multi-cluster tools for semiconductor manufacturing. In this paper, we study a decision-moving-done method of event driven simulation for multi-cluster tools. Based on this method, we are able to manage all activities identically in the simulation. The proposed event graph based simulation study can further be integrated into a pruning search algorithm to find the optimal robot scheduling sequence. Incorporated with simulation model, the search algorithm detects deadlocks and significantly reduces the computing time. A chemical-mechanical planarization (CMP) polisher is used as an example of the multi-cluster cluster tools to illustrate the proposed event graph based simulation and scheduling analysis.

A New Method to Determine the Tool Count of a Semiconductor Factory Using FabSim
Holger Vogt (Fraunhofer IMS)

Tool count optimization is mandatory for an efficiently organized semiconductor factory. This paper describes an efficient heuristic to determine the tool count using the compact fab simulator FabSim Interactive. A combination of the Simulated Annealing algorithm and the knowledge of toolset usage, which is gained by repeated simulation of the factory, results in a fast approach. There are no restrictions concerning multiple products and processes during optimization. A simple cost model (revenue per wafer out minus tool depreciation) yields the objective function to be maximized, tool count values per toolset are the decision variables, and a lot start sequence determines the fab throughput required. Depending on the factory size, optimization results may be available within a few hours of simulation time on a standard PC.

Wednesday 8:30:00 AM 10:00:00 AM
Semiconductor Factory Scheduling and Control

Chair: Theresa Roeder (U. of California, Berkeley)

Wafers in a 300-mm semiconductor fabrication facility are transported throughout the factory in carriers called front opening unified pods (FOUPs). Two standard capacities of FOUPs are 25 and 13 wafers. This paper describes a simulation study designed to compare the performance of a factory employing different FOUP capacities. The main performance measure considered is work-in-process (WIP) and the resulting cycle time. Batching policy, order arrival rate, average order size, the Automated Material Handling System (AMHS) and the number of batch tools largely effect the performance of the models. Most of the empirical results show that the 25-wafer FOUP capacity provides a lower WIP level in a moderately loaded semiconductor factory.

Intelligent Simulation-Based Lot Scheduling of Photolithography Toolsets in a Wafer Fabrication Facility
Amr Arisha and Paul Young (Dublin City University)

Scheduling of a semiconductor manufacturing facility is one of the most complex tasks encountered. Confronted with a high technology product market, semiconductor manufacturing is increasingly more dynamic and competitive in the introduction of new products in shorter time intervals. Lot scheduling within photolithography is a challenging activity where substantial improvements in factory performance can be made. The proposed scheduling methodology integrates two common approaches, simulation and artificial intelligence. Using detailed simulation modeling within a structured modeling method, a comprehensive model to characterize the photolithography process was developed. An artificial intelligence scheduler was then developed and integrated with the model with the goal of reducing Work-In-Process (WIP), setup time, and throughput time. The results have shown a significant improvement in lot cycle time as well as tool utilization, improved the throughput time by an average of 15% and is currently in use for scheduling the photolithography process.

Simulation-Based Advanced WIP Management and Control in Semiconductor Manufacturing
Kazuo Miyashita (National Institute of Advanced Industrial Science and Technology (AIST)), Tsukasa Okazaki (HItachi East Japan Solutions, Ltd.) and Hirofumi Matsuo (Kobe University)

We develop a hierarchical distributed production planning and control methodology, called DISCS, for a large and unstable semiconductor manufacturing process. The upper layer of DISCS periodically optimizes work-in-process inventory (WIP) levels to meet demands and sets a target WIP level for each workstation. One of key technologies required for the purpose is a fast simulation method to make the iterative optimization process tractable. In the lower layer, dispatching decisions are made at each workstation based on its target WIP level. Computational experiments using wafer fabrication process data show that DISCS, when compared with a traditional control method, succeeds in meeting the demand while keeping lower WIP levels. This indicates that DISCS is a promising methodology for production planning and control in semiconductor manufacturing.

Comparative Factory Analysis of Standard FOUP Capacities
Kranthi Mitra Adusumilli (University of Texas) and Robert L. Wright (International SEMATECH Manufacturing Initiative)

Wednesday 10:30:00 AM 12:00:00 PM
Semiconductor Factory Performance Evaluation

Chair: Oliver Rose (University of Würzburg)

This paper illustrates an example of the use of a metamodeling approach to simulation through an example of two real world semiconductor manufacturing systems. The metamodel used was from Yang et al. (2004) and has similarities to Cheng and Kleijnen (1999). The approach aims at reducing the amount of simulation work necessary to generate high quality cycle time-throughput (CT-TH) curves. The paper specifically focuses on demonstrating that, in practice, CT-TH curves can deviate significantly from forms currently assumed in the literature (Cheng and Kleijnen 1999).

A Queueing Network Approximation of Semiconductor Automated Material Handling Systems: How Much Information Do We Really Need?
Theresa M. Roeder (University of California, Davis), Nirmal Govind (Intel Corporation) and Lee W. Schruben (University of California, Berkeley)

Queueing networks are sometimes used to model material handling in flexible manufacturing systems. We explore the use of a closed queueing network model to approximate an intrabay automated material handling system (AMHS) in semiconductor manufacturing. Rather than solving the model analytically, we propose simulating it. Current industry models are very complex and require long development and run times. The simulated approximation can be used as an easy and fast alternative. To compare the approximation with the detailed models in use, we employ an information taxonomy to classify AMHS models based on the amount and types of information needed to model the system, and to obtain desired output. This classification aids modelers in determining the level of detail to incorporate in a model based on the objectives of the simulation study.

Capacity Analysis of Automated Material Handling Systems in Semiconductor Fabs
Michael E. Kuhl and Julie Christopher (Rochester Institute of Technology)

A critical aspect of semiconductor manufacturing is the design and analysis of material handling and production control polices to optimize fab performance. As wafer sizes have increased, semiconductor fabs have moved toward the use of automated material handling systems (AMHS). However, the behavior of AMHS and the effects of AMHS on fab productivity is not well understood. This research involves the development of a design and analysis methodology for evaluating the throughput capacity of AMHS. A set of simulation experiments is used to evaluate the throughput capacity of an AMHS and the effects on fab performance measures. The analysis uses SEMATECH fab data for full semiconductor fabs to evaluate the AMHS throughput capacity.

Nonlinear Regression Fits for Simulated Cycle Time vs. Throughput Curves for Semicondutor Manufacturing
Rachel T. Johnson, Feng Yang, Bruce E. Ankenman, and Barry L. Nelson (Northwestern University)