WSC 2005

WSC 2005 Final Abstracts

Semiconductor Manufacturing Track

Tuesday 3:30:00 PM 5:00:00 PM
Factory Simulation

Chair: John Fowler (Arizona State University)

Efficient Simulations for Capacity Analysis and Automated Material Handling System Design in Semiconductor Wafer Fabs
Jesus A. Jimenez, Gerald Mackulak, and John W. Fowler (Arizona State University)

The Automated Material Handling System (AMHS) must be designed effectively so that it never becomes a limiting factor for the capacity of 300mm wafer fabs. Ideally, a fully integrated fab simulation model (i.e. a model containing detailed modeling constructs for the production operations, the tools, the AMHS, and tool AMHS interactions) should be used in order to design the AMHS. However, the problem is that it takes too much time to simulate and analyze these models. Experimentation has demonstrated that certain capacity models with less detailed AMHS representations can generate accurate system predictions in comparison to the values produced by fully integrated models. Because these less detailed models run faster, we can thus assess efficiently the effects of an AMHS design configuration on equipment capacity. A case study comparing the computational efficiency and the quality of the performance predictions at different levels of detail will be presented.

A Framework for Standard Modular Simulation in Semiconductor Wafer Fabrication Systems
Jose A. Ramirez-Hernandez, Heshan Li, and Emmanuel Fernandez (University of Cincinnati), Swee Leong (National Institute of Standards and Technology (NIST)) and Charles R. McLean (National Institute of Standards and Technology)

This paper presents the application of a framework, proposed by the National Institute of Standards and Technology (NIST), for standard modular simulation in semiconductor wafer fabrication facilities (fabs). The application of the proposed framework resulted in the identification and specification of four different elements in the context of semiconductor fabs: (1) market sector, (2) hierarchical modeling levels, (3) simulation case studies, (4) models and data. An example of the application of the proposed simulation framework to a benchmark semiconductor fab model, the so-called "Mini-fab", is presented. In this example, evaluation of production performance under different workforces is studied. Current and future research is focused on the improvement of the proposed framework (e.g., design and testing of generic case studies).

A Discrete Event Simulation Model Simplification Technique
Rachel T. Johnson, John W. Fowler, and Gerald T. Mackulak (Arizona State University)

Cycle Time – Throughput curves (CT-TH), which plot the average cycle time versus start rate for a given product mix, are often used to support decisions made in manufacturing settings, such as the impact of proposed changes in start rate on mean cycle time. Discrete event simulation is often used to generate estimations of cycle time at a significant number of traffic intensities (start rates). However, simulation often requires long run lengths and extensive output analysis. In most manufacturing environments, the time and/or budget available for such simulations is limited. As demands for faster and more accurate results are required, alternative approaches to improving simulation efficiency must be investigated. This research seeks to develop a procedure for simplifying a detailed model into a fast (abstract) simulation model that achieves a statistically indistinguishable level of accuracy and precision. This technique has particular application in the simulation of semiconductor manufacturing facilities.

Wednesday 8:30:00 AM 10:00:00 AM
Factory Control

Chair: Lars Mönch (Technical University of Ilmenau)

Analysis of Production Control Methods for Semiconductor Research and Development Fabs Using Simulation
Vikram Ramamurthi, Michael E. Kuhl, and Karl D. Hirshman (Rochester Institute of Technology)

A semiconductor company must bring technology to the market as soon as its application is deemed feasible to be a leader in the industry. The goal of this paper is to investigate production control methods in semiconductor R&D fabs to minimize the time to market for the aforementioned technology. Simulation models of a representative R&D fab are run with different levels of bottleneck utilization, lot priorities, primary and secondary dispatching strategies and due date tightness as treatment combinations in a formally designed experiment. The fab performance measures are percent on time delivery, average cycle time, standard deviation of cycle time and average work-in-process. Fab characteristics are found to influence the application of dispatching rules. However, several dispatching rules are found to be robust across performance measures.

Simulation-based Assessment of Order Release Strategies for a Distributed Shifting Bottleneck Heuristic
Lars Mönch (Technical University of Ilmenau)

In this paper, we investigate the influence of several order release strategies on the performance of a distributed shifting bottleneck heuristic. The shifting bottleneck heuristic is a decomposition approach that solves the overall scheduling problem by solving a sequence of tool group scheduling problems and determines the overall solution by using a disjunctive graph. We discuss a distributed version of the original shifting bottleneck heuristic. By using a hierarchical approach we first assign planned ready and completion dates to all lots with respect to a certain work area where a work area is defined as a set of tool groups. We study several order release strategies. It turns out that the distributed shifting bottleneck heuristic performs well compared to dispatching rules only in high loaded job shops. We present the results of computational experiments.

Using Simulation Based Approach to Improve on the Mean Cycle Time Performance of Dispatching Rules
Chin Soon Chong and Malcolm Yoke Hean Low (SIMTech) and Appa Iyer Sivakumar and Kheng Leng Gay (Nanyang Technological University)

This paper presents a simulation based approach to improve on the mean cycle time performance of dispatching rules. The method applies recursive simulation technique on dispatching rules to search for new improved solutions for a set of job shop problems. Due to the nature of the recursive heuristic, performance criteria other than mean cycle time and various dispatching rules can be implemented into the recursive simulation framework without requiring too much effort. The performance of the proposed approach is compared to the underlying dispatching rules as well as a published tabu search procedure. The preliminary results show that the approach outperforms the underlying dispatching rules and is comparable to the tabu search procedure.

Wednesday 10:30:00 AM 12:00:00 PM
Tool Control

Chair: Olver Rose (Dresden University of Technology)

Scheduling Cluster Tools Using Filtered Beam Search and Recipe Comparison
Simon Oechsner (University of Würzburg) and Oliver Rose (Technical University of Dresden)

Cluster tools have gained a lot of importance in today’s semiconductor manufacturing. A cluster tool basically consists of several processing chambers in a mainframe, several load locks to insert wafer lots and a robot arm to move them. This means that these tools are able to work on more than one lot at the same time. Since the lot combination processed together can have an influence on the cycle times of these lots, scheduling is needed to ensure that the overall cycle times are kept low. In a previous work, we presented a method based on filtered beam search using slowdown factors as evaluation methods. Here, we will present another evaluation method based on recipe comparison that produces even better results. We will also show results of a beam width parameter study.

Optimizing Robot Algorithms with Simulation
Todd LeBaron (Brooks Automation) and Joerg Domasche (Infineon Technologies AG)

Maximizing equipment throughput on multi-chambered cluster tools is an ongoing objective for semiconductor fabs. The increasing use of dual-armed robots and the need to process multiple products simultaneously complicates this objective. Typically, when a new processing technology is introduced, one chamber inside the tool is dedicated to the new process, while the other chambers are assigned to run normal production wafers. This results in multiple wafer flows or “parallel routes” within the tool. Determining and implementing optimal robot schedulers to efficiently handle the complexities within the tool is key to maximizing equipment throughput. This paper introduces the components of a multi-chambered cluster tool and dis-cusses how simulation was used at Infineon to develop, test, and optimize efficient wafer selection rules. Several real-world cases are detailed and reported.

An Analysis: Traditional Semiconductor Lithography Versus Emerging Technology (Nano Imprint)
Walt Trybula (SEMATECH), Robert Wright and Kranthi Mitra Adusumilli (International SEMATECH Manufacturing Initiative) and Randy K Goodall (SEMATECH)

The introduction of emerging technologies into existing manufacturing facilities is not necessarily encouraged by the people responsible for the output of the facilities. Any “new” technology carries risks and people responsible for delivering manufactured products are, by nature, risk-adverse. This paper demonstrates the advantage of evaluating the impact of attempting to introduce a new technology into an existing facility before actually attempting the introduction. The first part of the analysis examines the impact on the total product delivery for a comparable volume of two facilities, one with the traditional processes and one with the new process replacing existing ones. Based on these results, a conclusion can be reached if there are sufficient benefits to consider pursuing the development and introduction of the new techniques. An example is employed that evaluates the introduction of nano-imprint.