WSC 2008

WSC 2008 Final Abstracts

MASM - Operational Modeling and Simulation Track

Monday 10:30:00 AM 12:00:00 PM
Simulation-Based Decision-Making

Chair: Gerald Weigert (Dresden University of Technology)

A Full-Factory Simulator as a Daily Decision-Support Tool for 300mm Wafer Fabrication Productivity
Sugato Bagchi (IBM T.J. Watson Research Center), Ching-Hua Chen-Ritzo (IBM T. J. Watson Research Center) and Sameer T Shikalgar and Michael Toner (IBM Systems and Technology Group)

We describe a discrete event simulator developed for daily prediction of WIP position in an operational 300mm wafer fabrication factory to support tactical decision-making. The simulator is distinctive in that its intended prediction horizon is relatively short, on the order of a few days, while its modeling scope is relatively large. The simulation includes over 90% of the wafers being processed in the fab and all process, measurement and testing tools. The model parameters are automatically updated using statistical analyses performed on the historical event logs generated by the factory. This paper describes the simulation model and the parameter estimation methods. A key requirement to support daily and weekly decision-making is good validation results of the simulation against actual fab performance. Therefore, we also present validation results that compare simulated production metrics against those obtained from the actual fab, for fab-wide, process, tool and product specific metrics.

Coping with Typical Unpredictable Incidents in a Logic Fab
Wolfgang Scholl (Infineon Technologies Dresden)

Within the last months the semiconductor plant of Infineon in Dresden has converted to a pure manufacturer of logic products. With it, premises for production control have changed to short and, first of all, predictable cycle times. Typical for a logic fab, intelligent performance monitoring and prediction methods have to be installed, coping scheduled and unscheduled disturbances. Most important method is transient fab simulation, giving a 3-months performance forecast based on actual line situation and planned changes in toolset and product mix. This continuous forecast has to be enriched with information to scheduled and unscheduled fab disturbances for just in time initiation of countermeasures in case of foreseeable excursions, e.g. changes in dispatching. In particular, breakdowns have to be analyzed from historical data to find typical patterns, for probability of occurrence and, especially, machine group specific behavior. This paper presents the procedure on the basis of three examples.

Experimental Study on Variations of Wipload Control in Semiconductor Wafer Fabrication Environment
Appa Iyer Sivakumar (Singapore-MIT Alliance), Chao Qi (Huazhong University of Science and Technology) and Andy Darwin (Singapore-MIT Alliance)

WIPLOAD Control has been proposed and evaluated as an effective job release control methodology. This paper presents a further simulation experimental study on two variations of WIPLOAD Control in semiconductor wafer fab environment. The first variation mechanism is to control separate WIPLOAD for each part type at a specified level under the situation when the type of job going to be released next can be controlled. The second variation is a mechanism with additional release control points along the production line. The performance of the WIPLOAD variations are compared with that of the original WIPLOAD Control and other existing release methods including CONWIP and Constant release in semiconductor manufacturing environment. The experimental results indicate that by breaking down the control of overall fab WIPLOAD into controlling WIPLOAD level for each part type, cycle time performance can be improved especially with respect to the standard deviation of cycle time.

Monday 1:30:00 PM 3:00:00 PM
Factory Scheduling

Chair: Lars Mönch (University of Hagen)

Simulation-Based and Solver-Based Optimization Approaches for Batch Processes in Semiconductor Manufacturing
Andreas Klemmt and Sven Horn (Electronics Packaging Laboratory), Gerald Weigert (Dresden University of Technology) and Thomas Hielscher (Qimonda)

Scheduling is one of the key factors for semiconductor fabrication productivity. Objectives like lot cycle time and throughput must be optimized to push the technological development and secure the existence on the rapid growing global market. But especially in the frontend the manufacturing process is dominated by cluster-tools and reentrance flows which makes a production planning and optimization very hard. The workflow here is mostly controlled only by dispatch rules. To get a further improvement in manufacturing planning strategies, there is an increasing request of exact or simulation-based solution methods for specified work centers or bottleneck machine groups. One example of this is the semiconductor oven process. Here, complex batch processes with a lot of restrictions have to be scheduled. A reduction of cycle time in this section by optimized manufacturing strategies has a great influence on all global optimization objectives. Two approaches are investigated in this paper.

Bee Colony Optimization Algorithm with Big Valley Landscape Exploitation for Job Shop Scheduling Problems
Li-Pei Wong, Chi Yung Puan, and Malcolm Yoke Hean Low (Nanyang Technological University) and Chin Soon Chong (Singapore Institute of Manufacturing Technology)

Scheduling is a crucial activity in semiconductor manufacturing industry. Effective scheduling in its operations leads to improvement in the efficiency and utilization of its equipment. Job Shop Scheduling is an NP-hard problem which is closely related to some of the scheduling activities in this industry. This paper presents an improved Bee Colony Optimization algorithm with Big Valley landscape exploitation as a biologically inspired approach to solve the Job Shop Scheduling problem. Experimental results comparing our proposed algorithm with Shifting Bottleneck Heuristic, Tabu Search Algorithm and Bee Colony Algorithm with Neighborhood Search on Taillard JSSP benchmark show that it is comparable to these approaches.

Impact of Qualification Management on Scheduling in Semiconductor Manufacturing
Carl Johnzén (STMicroelectronics), Stéphane Dauzère-Pérès (Ecole des Mines de Saint-Etienne), Philippe Vialletelle (STMicroelectronics) and Claude Yugma and Alexandre Derreumaux (Ecole des Mines de Saint-Etienne)

A qualification management software that proposes recipe qualifications on tools in toolsets for semiconductor manufacturing has been developed. The qualification proposals are based on flexibility measures that have been shown to model capacity allocation in semiconductor workshops. In this paper, qualifications are used in order to see how increased flexibility for the capacity allocation improve scheduling. For this a scheduler simulator for the photolithography area has been used. Tests prove that qualifications – if they are well managed – both enable the simulator to achieve better scheduling and enable toolsets to be less sensitive to tool breakdowns.

Monday 3:30:00 PM 5:00:00 PM
Queuing Models

Chair: Horst Zisgen (IBM Deutschland)

A Queueing Network Based System to Model Capacity and Cycle Time for Semiconductor Fabrication
Horst Zisgen and Ingo Meents (IBM Deutschland), Benjamin R. Wheeler (IBM) and Thomas Hanschke (Clausthal University of Technology)

In today's semiconductor business, wafer manufacturers are facing continuous pressure to accurately predict cycle time and tool utilization, gauge the impact of changes in capacity available and changes in product mix, and determine action plans to improve operational performance. Discrete Event Simulation (DES) is a widely used approach to perform such an analysis. However, DES has some inherent shortcomings for these planning tasks. Analytical models, like queueing networks, have much shorter response times and additional advantages compared to DES. But due to the complexity of semiconductor manufacturing systems (SMS) queueing models were not able to model all the peculiarities of those. This paper provides an overview of the IBM Enterprise Production planning and Optimization System (EPOS), a queueing network based system, which closes this gap. EPOS has been in use in the 300mm fabrication of IBM for more than 2 years and has turned out to be an invaluable tool.

Characterizing the Departure Process from a Two Server Markovian Queue: A Non-Renewal Approach
Guy L. Curry and Natarajan Gautam (Texas A&M University)

For large queueing network analysis the general computational approach is to utilize decomposition to facilitate computational tractability. To accomplish this individual analysis the input and output streams must be characte-rized. This usually is done via two-parameter characterizations: the process mean and a variance measure (most commonly the squared coefficient of variation SCV). In most approaches independent and identically distributed (i.i.d.) approximations are used. For multiple input streams and/or multiple (identical) servers, the assumptions of i.i.d. times between arrivals and, similarly, i.i.d. times between departures are particularly theoretically and computationally inaccurate. In this paper we develop a generator for the background multidimensional continuous time Markov chain associated with the inter-departure times for the associated multi-stream and multi-server Markovian queues (where inter-arrival times and service times are Coxian). This generator allows for the computation of the moments of the departure process and the lag-k correlations between successive k-separated departures.

Queueing Models for Single Machine Manufacturing Systems with Interruptions
Kan Wu, Leon F. McGinnis, and Bert Zwart (Georgia Tech)

Queueing theory is a well-known method for evaluating the performance of manufacturing systems. When we want to analyze the performance of a single machine, M/M/1 queues or approximations of G/G/1 queues often are considered a proper choice. However, due to the complex nature of interruptions in manufacturing, the appropriate model should be selected carefully. This paper proposes a systematic way to classify different kinds of interruptions seen in a single machine system. Queueing models for each category are proposed, and event classifications are compared from both the SEMI E10 and queueing theory points of view.

Tuesday 8:30:00 AM 10:00:00 AM
Panel Discussion

Chair: John Fowler (Arizona State University)

Modeling and Analysis of Semiconductor Manufacturing in a Shrinking World: Challenges and Successes
Chen-Fu Chien (TSMC), Stéphane Dauzère-Pérès (Ecole des Mines de Saint-Etienne), Hans Ehm (Infineon Technologies AG), John W. Fowler (Arizona State University), Zhibin Jiang (Shanghai Jiao Tong University), Shekar Krishnaswamy (AMD), Lars Moench (University of Hagen) and Reha Uzsoy (North Carolina State University)

A panel session on the role of modeling and analysis in semiconductor manufacturing in a shrinking world is presented. Therefore, two participants are from Asia, two from Europe, and two from US and there are two panel organizers/moderators (Fowler and Mönch). One panelist from each continent is from industry and one from academia. Only initial position statements are included in the proceedings. However, these initial statements form the basis for the panel discussion. The statements of the panelists from industry relate to modeling and analysis problems found in their own companies. The position statements of the panelists from academia describe the role that modeling and analysis is expected to play in their current and ongoing research in semiconductor manufacturing. Furthermore, their views on the challenges and successes of modeling and analysis in a globalized world are also included.

Tuesday 10:30:00 AM 12:00:00 PM
Modeling of Batching Tools

Chair: Reha Uzsoy (North Carolina State University)

Online Control of a Batch Processor with Incompatible Job Families under Correlated Future Arrivals
John Benedict Tajan (Singapore-MIT Alliance), Appa Iyer Sivakumar (Singapore-MIT Alliance (Nanyang Technological University)) and Stanley Gershwin (Singapore-MIT Alliance (Massachusetts Institute of Technology))

Oxidation and diffusion ovens in wafer fabrication are batch processors; only jobs with identical job families can be processed together. Initially, we use simulation to show that a heuristic based on Model Predictive Control (MPC), with properly selected parameters, has up to 16.67% lower mean cycle time than NACHM (a look-ahead method), under uncorrelated arrivals. Controlling upstream processors according to the anticipated needs of the batch processor may result in correlated families for successive arrivals. Increasing correlation between arrivals almost always significantly reduces the mean cycle time, for both policies. Furthermore, NACHM improves at a faster rate than the MPC-based heuristic. Thus, when the correlation is high (0.7) and the traffic intensity low (0.5), the MPC-based heuristic, has longer mean cycle time (from 1.92% to 9.47%) than NACHM. Our results highlight the benefits of constraining the upstream processor according to the anticipated needs of the batch processor.

Time-Limited Next Arrival Heuristic for Batch Processing and Setup Reduction in a Re-Entrant Environment
Stephen Murray (Dublin City University), Steve Sievwright (Intel Ireland Ltd.) and John Geraghty and Paul Young (Dublin City University)

This paper presents a new batch scheduling heuristic - the Time-Limited Next Arrival heuristic for batch processing and setup reduction (TLNA). This heuristic has been defined for a batch processing machine group in a re-entrant manufacturing environment where setups are sequence-dependent. When making the scheduling decision, TLNA takes into account future arrivals based on a user-defined wait time. A series of experiments is conducted on a discrete event simulation model to determine the impact of this wait time. A total cost function is used to combine two conflicting performance measures (total item queuing time and total machine running time) into one. All TLNA wait time scenarios are compared to the Next Arrival Control Heuristic for Multiple products and Multiple machines (NACHMM). The experiments presented show that there is a wait time that minimises the total operational cost. TLNA outperforms NACHMM with regard to all performance measures except total queuing time.

Simulation Analysis of Semiconductor Manufacturing with Small Lot Size and Batch Tool Replacements
Kilian Schmidt (AMD Saxony LLC & Co. KG) and Oliver Rose (Dresden University of Technology)

Long cycle times in semiconductor manufacuring represent an increasing challenge for the industry and lead to a growing need of break-through approaches to reduce it. Small lot sizes and the conversion of batch processes to mini-batch or single-wafer processes are widely regarded as a promising means for a step-wise cycle time reduction. However, there is still a lack of comprehensive and meaningful studies. In this paper we present first results of our modeling and simulation assessment. Our simulation analysis shows that small lot size and the replacement of batch tools with mini-batch or single wafer tools are beneficial but lot size reduction lacks persuasive effectiveness if reduced by more than half.

Tuesday 1:30:00 PM 3:00:00 PM
Equipment Modeling

Chair: Julie Christopher (IBM Microelectronics)

A Review of Scheduling Theory and Methods for Semiconductor Manufacturing Cluster Tools
Tae-Eog Lee (KAIST)

Cluster tools, which combine several single-wafer processing modules with wafer handling robots in a closed environment, have been increasingly used for most wafer fabrication processes. We review tool architectures, operational issues, and scheduling requirements. We then explain recent progress in tool science and engineering for scheduling and control of cluster tools.

Study of Optimal Load Lock Dedication for Cluster Tools
Julie Christopher (IBM Microelectronics)

Cluster or chamber tools are often used in the semiconductor industry. In a research environment, moving to smaller device dimensions requires experimentation with new chamber types and materials to overcome challenges with Moore’s Law. To make the most of expensive mainframes and clean room floor space multiple chamber types can be placed on one mainframe. Although this type of configuration can reduce cost while evaluating new complex processes, the efficiency of the tool as a whole can be drastically reduced. A major bottleneck within tools configured with multiple process chambers can be the load locks. These load locks are the single wafer entry point into the vacuum chamber. This paper will show the effect of load lock dedication on a sample multi-process chamber tool.

Simulation Analysis of Cluster Tool Operations in Wafer Fabrication
Amit Kumar Gupta (Birla Institute of Technology and Science - Pilani, Hyderababd Campus), Peter Lendermann (D-SIMLAB Technologies Pte Ltd) and Sivakumar Appa Iyer and John Priyadi (Nanyang Technological University)

Cluster tools have been one of the proposed alternatives to improve operations performance in semiconductor fabrication. The benefits include high yield throughput, less contamination and less human involvement. Perkinson et al. (1994, 1996) developed analytical models to predict the minimum theoretical time required to complete the cycle in a cluster tool. This paper addresses the verification of these analytical models using simulation. Two simulation models were developed – one with simple configuration and another one that incorporates parallel chambers. The implementation of parallel chambers for the longest process in the cluster tool is tested as the potential area of performance improvement.

Tuesday 3:30:00 PM 5:00:00 PM
AMHS Modeling and Simulation

Chair: Jens Zimmerman (University of Hagen)

An Analytical Model for Conveyor Based AMHS in Semiconductor Wafer Fabs
Dima Nazzal (University of Central Florida), Andrew Johnson (Texas A&M University), Hector J. Carlo (University of Puerto-Rico-Mayagüez) and Jesus A. Jimenez (Texas State University)

This paper proposes an analytical model useful in the design of conveyor-based Automated Material Handling Systems (AMHS) to support semiconductor manufacturing. The objective is to correctly estimate the work-in-process on the conveyor and assess the system stability. The analysis approach is based on a queuing model, but takes into account details of the operation of the AMHS including turntables. A numerical example is provided to demonstrate and validate the queuing model over a wide range of operating scenarios. The results indicated that the analytical model estimates the expected work-in-process on the conveyor with reasonable accuracy.

A Simulation Based Approach for Supporting Automated Guided Vehicles (AGVs) Systems Design
Elisa Gebennini, Sara Dallari, Andrea Grassi, Giuseppe Perrica, Cesare Fantuzzi, and Rita Gamberini (Dipartimento di Scienze e Metodi dell’Ingegneria - University of Modena and Reggio Emilia)

Automated Guided Vehicle (AGV) logistic handling systems are widely adopted when high transportation capacity and quality of service are the most important characteristics to reach. A large number of mathematical approaches have been developed in years to address AGV systems design and control. Nevertheless, proper performance estimations have to consider the peculiar aspects of the real environment in which the AGV system operates. A simple and effective approach to the stochastic features modelling is the discrete event simulation of the real system. This paper presents a conceptual approach that lead the analyst to set up consistent simulative models to address AGV systems design and performance estimation when applications in end-of-line logistics are considered.

Determining an Appropriate Number of Foups in Semiconductor Wafer Fabrication Facilities
Jens Zimmermann and Lars Moench (University of Hagen), Scott J Mason (University of Arkansas) and John W. Fowler (Arizona State University)

In this paper, multiple orders per job type formation and release strategies are described for semiconductor wafer fabrication facilities (wafer fabs). Different orders are grouped into one job because orders of an individual customer very often fill only a portion of a Front-Opening Unified Pod (FOUP). A FOUP is assigned to each job and is used to move the job throughout the wafer fab after the job formation. We determine an appropriate number of FOUPs for a given order release rate that will yield acceptable values for on-time delivery performance, cycle time, and throughput via discrete event simulation.

Wednesday 8:30:00 AM 10:00:00 AM
Simulation Applications

Chair: Stéphane Dauzère-Pérès (Ecole des Mines de Saint-Etienne)

Decision Making and Forecasting with Respect to Risk: A Simulation Study for a Setup-Problem
Martin Romauch (Infineon Technologies), Christian Almeder (University of Vienna) and Walter Laure and Georg Seidel (Infineon Technologies)

In this paper, the impact of timing a setup operation on the work-in-process and cycle time is investigated. Using a small example of an reentrant production system, it is shown that there is a tradeoff between reducing the average work-in-process inventory and guaranteeing a smooth operation of the system. Furthermore it is shown, that an early setup may lead to an increased variance of the cycle time, but regarding the number of lots with an extreme excess of cycle time the timing decision has only a minor influence.

An Experimental Study of an Iterative Simulation-Optimization Algorithm for Production Planning
D. Fatih Irdem, N. Baris Kacar, and Reha Uzsoy (North Carolina State University)

It is well known from queueing and simulation models that cycle times in capacitated production systems increase nonlinearly with resource utilization, which poses considerable difficulty for the conventional linear programming (LP) models used for this purpose. Hung and Leachman (1996) propose a highly intuitive iterative approach where a detailed simulation model of the production facility is used to estimate flow time parameters used in an LP model. We examine the convergence characteristics of this method under different experimental conditions, and conclude that it is hard to determine precisely when the method converges.

Analysis of Multiple Process Flows in an Asic Fab with a Detailed Photolithography Area Model
Kamil Erkan Kabak and Cathal Heavey (University of Limerick) and Vincent Corbett (Analog Devices)

ASIC fabs are characterized by multiple process flows. This is mainly due to the highly diversified product portfolios within such fabs. In this study, we first examined the cycle time for individual process flows in a medium volume ASIC fab. We compared these process flows in terms of overall cycle time and using a cycle time index. Secondly, focusing on photolithography we developed a simulation model that employs cycle time data to analyze the impacts of process flow diversity. Thirdly, we used this model to examine the impact on cycle time of changing the volumes of wafer starts on different process flows. The detailed results of simulation experiments along with the concluding remarks are given at the end of the study.

Wednesday 10:30:00 AM 12:00:00 PM
Modeling Approaches and Optimization Formulations

Chair: Chen-Fu Chien (National Tsing Hua University)

An Optimization Framework for Waferfab Performance Enhancement
Boon Ping Gan (D-SIMLAB Technologies)

A typical wafer fab requires numerous decisions for daily operations. Even small decisions on system configurations may have significant impact on the overall fab performance. One of the most critical performance measure is cycle time, where just one day of reduction could represent significant cost savings. In this paper we describe an automated simulation-based optimization method to improve fab configurations. We illustrated our method through a case study that involves optimization of multiple decision variables in a wafer fab. The objective of the optimization is to reduce the cycle time. We show the potentials of such an optimization through achieving an improvement of 15% in cycle time for a furnace toolset.

An Indirect Workforce (Re)allocation Model for Semiconductor Manufacturing
Chen-Fu Chien (National Tsing Hua University), Wen-Chih Chen (National Chiao Tung University) and Shao-Chung Hsu (National Tsing Hua University)

Semiconductor industry is a capital intensive and knowledge intensive industry, in which human resource management and human capital enhancement is increasingly important. To maintain competitive human resource, it is critical to develop a decision framework for headcount planning and workforce allocation for indirect labors. This study aims to develop a model for allocating indirect workforce among semiconductor fabrication facilities to meet expected outputs and labor productivity improvement. Workforce allocation and reallocation based on the overall corporate workforce level is essential so that the shortage or exceed workforce will be balanced among different production sites. The key to achieve this purpose is the proper understanding of real requirements of each production site according to its corresponding tasks assigned. Non-parametric activity analysis approach is used for the workforce requirement estimation given delegated tasks. The estimation is based on the best performance from the past with adjustments reflecting the expected productivity growth.

Multi-Product Lot Merging/Splitting Algorithms for a Semiconductor Wafer Fabrication
June-Young Bang, Jae-Hun Kang, Bong-Kyun Kim, and Yeong-Dae Kim (KAIST)

This paper focuses on a lot merging/splitting problem in a semiconductor wafer fabrication facility. In the fab, two or more lots can be merged into a single lot if routes and all the processing conditions of the lots are the same for a number of subsequent operations, and the merged lot is split into the original lots at the point where the routes or processing conditions become different. We suggest lot merging/splitting algorithms to reduce the total tardiness of orders and the cycle times of the lots. The suggested algorithms are evaluated through a series of simulation experiments and the result shows that the algorithms work better than a method used in a real fab.