WSC 2008 Final Abstracts

Economic Efficiency Analysis of Wafer Fabrication Facilities
Wen-Chih Chen (National Chiao Tung University) and Chen-Fu Chien and Ming-Hsuan Chou (National Tsing Hua University)

Abstract:
Semiconductor industry is competitive, in which efficiently utilizing resources to provide products and services is essential for maintaining competitive advantages. Knowing whether the resource is properly utilized is the foundation for future improvements and/or decision making. This study aims to propose an economic efficiency study on fabrication operations. We develop a two-stage overall efficiency model, which clearly defines and explains the "real" performance of fab production operations and the non-production issues. The model thus provides an overall performance index while considering different aspects. A single performance index can used to evaluate and rank the performance for period review. Furthermore, according to a real case, an ex post relative efficiency analysis is conducted and the initial results are reported. The case study can help providing diagnosis for inefficient production facilities and identifying best practices of efficient production units.

Using Little's Law to Estimate Cycle Time and Cost
Kristin Rust (Advanced Micro Devices)

Abstract:
Well designed models can provide timely answers and summarize understanding of complex systems. Simple use cases can illustrate the applicability and inferences possible with even the most general models. This paper uses Little’s Law to demonstrate the prediction of fab operating conditions and associated cost implications.

Pricing Decision and Lead Time Setting in a Duopoly Semiconductor Industry
I-Hsuan Hong, Hsi-Mei Hsu, Yi-Mu Wu, and Chun-Shao Yeh (National Chiao Tung University)

Abstract:
Pricing and lead time setting are two important decisions in semiconductor foundry industries. This research considers the competition of a duopoly market consisting of two make-to-order firms in semiconductor foundry industries and presents a model to determine the equilibrium price and lead time of these two competing firms where each firm maximizes its own revenue and is subject to its own constraints in a duopoly market. In the model, customer mean demand rates of two competing firms are assumed as functions of committed lead times and prices provided by these two firms and the market. Furthermore, this paper utilizes a simulated procedure to verify the equilibrium price and lead time obtained by the analytical model presented in this paper.

Linear Inflation Rules for the Random Yield Production Control Problem with Uncertain Demand: Analysis and Computations
Woonghee Tim Huh (Columbia University) and Mahesh Nagarajan (University of British Columbia)

Abstract:
Since the dawn of wafer fabrication and the production of microelectronic parts a fundamental characteristic of this environment has been uncertainty in production yields and in demand for product. The impact of the uncertainty is so prevalent that even deterministic models in practice have incorporated some allowance for uncertainty through features such as date effective yields, moving average capacity, etc. In this paper, we propose a simple heuristic approach for the inventory control problem with stochastic demand and multiplicative random yield. Our heuristic tries to find the best candidate within a class of policies which are referred to in the literature as the linear inflation rule (LIR) policies. Our approach is computationally fast, easy to implement and intuitive to understand. Moreover, we find that in a significant number of instances our heuristic performs better than several other well-known heuristics that are available in the literature.

A Contract of Purchase Commitments on Shared Yields as a Risk-Sharing Mechanism among Fabless-Foundry Partnership
Yi-Nung Yang (Chung Yuan Christian University) and Shi-Chung Chang (National Taiwan University)

Abstract:
This paper develops a simple cooperative-game model for an alliance with a design house and a foundry in a semiconductor supply chain. In particular, we attempt to investigate an emerging observed type of contracts among fabless-foundry partnership. It is termed the purchase commitments on shared yields contract. We emphasize the risk-sharing aspect on the contract by explicit modeling risk into the fabless and foundry's objective functions. It is shown that the optimal share of yields depends on two parties' expectations on prices of the products, risk-aversion, and scales of production. The optimal share is not directly related to the both firms' marginal cost of production. That is, this contract is a cost-invariant contract. A Nash bargaining solution for the wholesale price under this contract between fabless and foundry is also proposed.

Priority Mix Planning for Cycle Time-Differentiated Semiconductor Manufacturing Services
Shi-Chung Chang, Shin-Shyu Su, and Ke-Ju Chen (National Taiwan University)

Abstract:
Semiconductor fabs often offer manufacturing service of multiple priorities in terms of cycle time-based X-factor targets (XFTs) and fab production must be planned accordingly. This paper studies a priority mix planning (PMP) problem that determines the wafer release rates of individual priorities to maximize fab profit subject to XFT and capacity constraints. It is formulated as a nonlinear programming problem, where the constraints integrate an extended M/G/m:PR queue approximation with contribution theory-based network for modeling how X-factors of individual priorities are affected by priority mix and fab capacity utilization. It is then demonstrated over a realistic fab example that PMP problem can be solved for effectively planning priority mix and machine tool capacity utilization to provide cycle-time differentiated manufacturing services.

Solving Volume and Capacity Planning Problems in Semiconductor Manufacturing: A Computational Study
Christoph Habla and Lars Moench (University of Hagen)

Abstract:
In this paper, we suggest a linear programming formulation that allows for solving volume and capacity planning problems in semiconductor manufacturing systems. We assume a general product structure that includes commodities, custom products, finished products between these two extreme classes, and several types of unfinished products. Computational experiments with respect to the required level of detail of bottleneck modeling are performed. Furthermore, we investigate the sensitivity of the model with respect to noisy demand data. It turns out that the number of modeled bottleneck is not crucial and that our approach can treat noisy demand data appropriately.

The Ongoing Challenge – An Accurate Assessment of Supply Linked to Demand to Create an Enterprise-Wide End to End Detailed Central Supply Chain Plan
Ken Fordyce, John Milne, Alfred Degbotse, Robert Orzell, Robert Rice, and Chi-Tai Wang (IBM)

Abstract:
Organizations can be viewed as an ongoing sequence of loosely coupled decisions where current and future assets are matched with current and future demand across the demand-supply network at different levels of granularity ranging from a placing a lot on a tool to an aggregate capacity plan across a five year horizon. Since the early 1990s detailed enterprise wide central planning has become a key member of this “decision suite.” Despite its importance, most organizations execute central planning with “limited levels of accuracy or intelligence.” Early in the evolution of “central planning engines” IBM determined that “extended accuracy” was an important component of supply chain efficiency and customer satisfaction and made a substantial investment to develop a central planning engine which could handle the scope (complexity) and scale (size) of large organizations. This presentation covers the value from this investment and the technical details of combining heuristics and optimization.

Simulation Based Planning and Scheduling System for TFT-LCD Fab
Bum C. Park and Eui S. Park (Samsung Electronics Co. Ltd.), Byoung K. Choi (KAIST), Byung H. Kim (VMS Solutions Co. Ltd.) and Jin H. Lee (KAIST)

Abstract:
In a typical LCD factory, a large number of product types are produced concurrently, 24 hours a day and 365 days a year, and there exist various constraints and re-entrant flows in the manufacturing processes. As a result, efficient planning and scheduling of LCD production is a big challenge. Presented in this paper is a simulation-based DPS (daily planning & scheduling) system that was developed by the authors and is being used in a modern LCD Fab in Korea. Also presented in the paper are a business architecture of LCD production management, internal structure of the DPS system, and Fab scheduling logic. The DPS system was installed at a large-size LCD Fab in 2006, and the system has been successfully used for two years leading to a considerable increase in on-time production of LCD panels and a sharp decrease in turn-around time.

Technology That Upsets the Social Order – A Paradigm Shift in Assigning Lots to Tools in Wafer Fabricator - The Transition from Rules to Optimization
Richard Burda (IBM), Robert Bixby and Vincent Gosselin (ILOG) and Ken Fordyce (IBM)

Abstract:
Historically the dominant decision technology to make dispatch decisions was “rules” which involves the following basic computational mechanisms: merge, select, sort, and if/then/else in a decision tree. Although rules do a reasonable job they fundamentally lack a robust ability to: (a) look across time, (b) look across tools at a tool set, (c) create an anticipated sequence of events at a tool set over some time horizon, (d) establish a formal metric and (f) search alternatives. However, standard wisdom was the rapid pace of change and short time interval between dispatch decisions precluded the use of optimization to build dispatch applications. Although this barrier was legitimate in the 1980s and most of the 1990s based on limitations in hardware and software (algorithms); the real barrier today is cultural; not technical. From 2004-2007, IBM and ILOG jointly worked to deploy the ILOG optimization product FPO to key tools sets in IBM’s 300mm fab resulting in substantial improvements in performance and significantly reduced overhead to adapt to changing circumstances. This paper will cover the fundamentals of the paradigm shift.

Scheduling a Multi-Chip Package Assembly Line with Reentrant Processes and Unrelated Parallel Machines
Sang-Jin Lee and Tae-Eog Lee (KAIST)

Abstract:
A multi-chip package(MCP) consists of several chip modules in a single package. We consider a scheduling problem for assembling MCPs. In order to assemble anMCP, a lot should repeat assembly process stages such as die attach and wire bonding as many as the number of chips to be assembled. The two key process stages have many parallel machines of various types. A machine processes different types of MCP lots with significant setup times. We therefore should limit the number of setups significantly while not sacrificing the on-time delivery performance much. We propose scheduling strategies of appropriately allocating the machine capacity to products and lots depending on the production progress of products and lots. We report experimental performances of the proposed methods.

Framework for Execution Level Capacity Allocation Decisions for Assembly – Test Facilities Using Integrated Optimization - Simulation Models
Shrikant Jarugumilli and Mengying Fu (Arizona State University), Naiping Keng and Chad DeJong (Intel Corporation) and Ronald Askin and John Fowler (Arizona State University)

Abstract:
We present a framework for capacity allocation decisions for Assembly-Test (A-T) facilities that is comprised of an optimization model and a simulation model. The optimization and simulation models are used iteratively until a feasible and profitable capacity plan is generated. The models communicate using an automated feedback loop and at each iteration the model parameters are adjusted. We describe the role of the optimization model, the simulation model and the feedback loop. Once the capacity plan is generated, it is passed down to the shop-floor for implementation. Hence, decision makers can develop accurate and more profitable execution level capacity plans using the integrated model which utilizes both optimization and simulation models. In this paper, we focus on the optimization model for capacity planning for the entire A-T facility at the individual equipment (resource) level for a two-week planning period and briefly discuss the simulation and the adjustment model.

Managing WIP and Cycle Time with the Help of Loop Control
Steffen Kalisch, Robert Ringel, and Joerg Weigang (AMD Saxony LLC & Co. KG)

Abstract:
As an adaptation of the CONWIP concept, AMD has developed a heuristic approach to control the WIP in its wafer fabrication facilities (fabs). The so called “Loop Control” concept helps to utilize the installed equipment in an efficient way and reduces the overall cycle time. Two dynamic constraints (the WIP-Limit and the THP-Limit) are defined to limit the WIP (work in progress) per photo layer and to tackle high WIP situations at individual operations inside a photo layer. Loop Control has been evaluated with help of a fab simulation study prior to implementation in the fab dispatching system. Since its development three years ago, this system operates successfully in the AMD Dresden fabs.

High Speed Semiconductor Fab Simulation for Large, Medium and Small Lot Sizes
Peter C Bosch (Highpoint Software Systems, LLC) and Robert L. Wright (International SEMATECH Manufacturing Initiative)

Abstract:
This paper describes an analysis performed to assess the fidelity, scalability, and performance of the Sage® Fab Advisor™ semiconductor fab simulation engine executing two years of fab operations across a range of lot sizes. We describe the demand and fab operations models used, as well as the tools and methodology used in conducting the analysis. Our results were validated against a well-known model running on a well-known toolset, showing performance to be very competitive with that model. Further, we show that our engine’s performance, running this model, scales almost linearly from 25 wafer lot sizes down to single wafer lot sizes. That is, simulation time increases roughly linearly with respect to the number of lots being processed.