WSC 2009 Final Abstracts

Equipment Models for Fab Level Production Simulation: Practical Features and Computational Tractability
James Robert Morrison (KAIST)

Abstract:
Equipment models used in fab-level simulation do not typically include features such as internal wafer buffers and setups that depend on wafer locations inside the tool. Such features are especially important to system performance in the presence of smaller lot sizes and greater product diversity. In this paper, we provide an introduction to flow line models that allow one to incorporate these key practical behaviors. We then develop flow line models for clustered photolithography tools and conduct simulations to assess the quality of the models. Despite the fact that the models only incorporate wafer transport robots via a constant addition to the process time, they can be quite accurate. When tested against data from a clustered photolithography tool in production, the model predictions for throughput and cycle time were within 1% and 4%, respectively. The computational requirements are about one order of magnitude less than is otherwise possible.

Evaluation of Modeling, Simulation and Optimization Approaches for Work Flow Management in Semiconductor Manufacturing
Robert Kohn, Daniel Noack, Marcin Mosinski, Zhugen Zhou, and Oliver Rose (Dresden University of Technology)

Abstract:
Work flow management is one of the key elements that bias the economic competitive position of a fabrication facility, especially in semiconductor manufacturing. This paper presents the goals, methods and challenges of our collaborative project with partners in semiconductor industry. The project activities concern topics in the disciplines of modeling, simulation and optimization classed among work flow management. Our goal is to evaluate suitable methods in the area of modeling, simulation and optimization in use cases given by reality. This project considers future performance prediction using different simulation techniques. In addition several optimization approaches will be evaluated in this project.

Simulation of a Full 300mm Semiconductor Manufacturing Plant with Material Handling Constraints
Jean-Etienne Kiba (STMicroelectronics - Ecole des Mines de Saint-Etienne), Stephane Dauzere-Peres and Claude Yugma (Ecole des Mines de Saint-Etienne) and Gilles Lamiable (STMicroelectronics)

Abstract:
Generally, simulation models encountered in the literature in the context of semiconductor manufacturing are obtained with many assumptions (aggregations) and from partial model simulation of the facility (also called fab). The results obtained can be satisfactory for certain types of studies but, when precise results and understanding of the detailed behavior of local or global parts of the fab are needed, these simplifications may no longer be adequate. A more detailed model and a full-scale simulation are then needed. This article presents a detailed simulation model of the production system and Automated Material Handling System for a 300 mm semiconductor plant. Some of the studies performed with this model are discussed.

Cycle Time Distributions of Semiconductor Workstations Using Aggregate Modeling
Casper Veeger, Pascal Etman, and Jacobus Rooda (Eindhoven University of Technology) and Joost van Herk (NXP Semiconductors Nijmegen)

Abstract:
Recently an aggregate modeling method has been developed to predict cycle time distributions as a function of throughput for manufacturing workstations with dispatching. The aggregate model is a single-server representation of the workstation with a workload-dependent process time distribution, and a workload-dependent overtaking distribution. The process time and overtaking distribution can be determined from arrival and departure events measured from the workstation at the factory floor. In this paper, we validate the proposed method in the context of semiconductor manufacturing. In particular we consider a lithography workstation. First, we present a simulation case that demonstrates the accuracy of the aggregate model to predict cycle time distributions. Second, we apply the aggregate modeling method to a case from semiconductor industry, and illustrate how the method performs using arrival and departure data obtained from the manufacturing execution system.

The Impact of Priority Generations in a Multi-Priority Queueing System - A Simulation Approach
A. Krishnamoorthy (Kochi University of Science and Technology), Viswanath Narayanan (Government Engineering College) and Srinivas R. Chakravarthy (Kettering University)

Abstract:
In this paper, we consider a preemptive (multiple) priority queueing model in which arrivals occur according to a Markovian arrival process. An arriving customer belongs to priority type i with a certain probability. The highest priority, labeled as 0 is generated by other priority customers while waiting in the system and not otherwise. Waiting priority customers can turn into other priority types or highest priority one. The waiting spaces for all but the lowest priority type are assumed to be finite. At any given time, the system can have at most one highest priority customer. Customers are served on a first-come-first-served basis within their priority by a single server and the service times are assumed to follow a phase type distribution that may depend on the customer priority type. This queueing model is simulated and the results for a few scenarios are presented.

A Simulation-Based Approximate Dynamic Programming Approach for the Control of the Intel Mini-Fab Benchmark Model
Jose A. Ramirez-Hernandez and Emmanuel Fernandez (University of Cincinnati)

Abstract:
This paper presents initial results on the application of a simulation-based Approximate Dynamic Programming (ADP) for the control of the benchmark model of a semiconductor fab denominated the Intel Mini-Fab. The ADP approach utilized is based on an Average Cost Temporal-Difference TD($\lambda$) learning algorithm and under an Actor-Critic architecture. Results from simulation experiments, on which both policies generated via ADP and commonly utilized dispatching rules were utilized in the Mini-Fab, demonstrated that ADP yielded policies that provided a good performance in average Work-In-Process and average Cycle Time with respect to the dispatching rules considered.

A Bottleneck Detection and Dynamic Dispatching Strategy for Semiconductor Wafer Fabrication Facilities
Zhugen Zhou and Oliver Rose (Dresden University of Technology)

Abstract:
According to the Theory of Constraints (TOC), the performance of a complex manufacturing system such as semiconductor wafer fabrication facility (wafer fab) is mainly determined by its bottleneck. In this paper, we investigate a bottleneck detection and corresponding dynamic dispatching strategy to regulate the workload of the bottleneck and non-bottleneck machines, in order to prevent bottleneck starvation and non-bottleneck with a high work in process (WIP) occurrence. The simulation results indicate that the proposed method achieves improvement with respect to average cycle time, cycle time variance and on time delivery compared with the classical dispatching strategies such as First In First Out (FIFO), Critical Ratio (CR).

Integer Programming-Based Real-Time Scheduler in Semiconductor Manufacturing
Myoungsoo Ham (Arizona State University), Young Hoon Lee (Yonsei University) and John W. Fowler (Arizona State University)

Abstract:
This paper demonstrates how an integer programming-based real-time scheduling heuristic approach can be applied for semiconductor manufacturing. Two integer programming formulations of a simplified version of this problem are proposed to model (1) a full-enumeration scheduling problem which minimizes the makespan (Cmax), and (2) a real-time scheduling problem which simply maximizes job assignments at the current state. The real-time scheduler’s overall effectiveness in terms of solution quality and run time is evaluated through computer experiments. The real time scheduler is based on an iterative procedure to calculate the makespan, where a simulator is developed to read the integer programming output and to update the job and machine information at each state. The experimental study shows how a well-defined integer programming-based real-time scheduling heuristic can generate a near-optimal solution.

A Greedy Heuristic for Locating Crossovers in Conveyor-Based AMHS in Wafer Fabs
Andrew Johnson (Texas A&M University), Hector J. Carlo (University of Puerto Rico-Mayaguez), Jesus Alejandro Jimenez (Texas State University-San Marcos) and Dima Nazzal and Vernet Lasrado (University of Central Florida)

Abstract:
Finding the optimal layout of Automated Material Handling Systems (AMHS) is critical for the design of next generation semiconductor wafer fabs. This paper proposes a greedy heuristic to determine the configuration of a conveyor-based AMHS featuring turntables and crossovers. Using a conveyor-based analytical model, the heuristic identifies the crossover that provides the greater benefit in terms of work-in process and delivery time reduction. The virtual SEMATECH 300 mm fab is used to demonstrate the application of the heuristic. Numerical results show that adding crossovers reduced the system’s delivery time by up to 22-percent in the scenarios under consideration.

Heuristic Based Scheduling System for Diffusion in Semiconductor Manufacturing
Tanju Yurtsever (Freescale Semiconductor, Inc.), Erhan Kutanoglu (The University of Texas at Austin) and Jennifer Johns (Freescale Semiconductor, Inc.)

Abstract:
This paper addresses the scheduling of lots in a specific wafer fabrication area, called diffusion, where scheduling of lots interact with batching, equipment dedication and queue time constraints. Realizing the difficulty of solving the underlying mathematical program optimally, we develop a heuristic to regularly schedule the lots available in the area in real time. The pa-per explains the user interface and implementation issues as well as the details of the heuristic logic. The results obtained from production in a wafer fabrication facility to date show high user compliance, improved predictability and visibility of the overall schedule, and improved operational performance including reduced cycle times and queue time violations.

A Comparison of MIP-Based Decomposition Techniques and VNS Approaches for Batch Scheduling Problems
Andreas Klemmt and Gerald Weigert (Technische Universität Dresden), Christian Almeder (University of Vienna) and Lars Mönch (University of Hagen)

Abstract:
This research is motivated by a scheduling problem found in the diffusion and oxidation areas of semiconductor wafer fabrication facilities. With respect to some practical motivated process constraints, like equipment dedication and unequal batch sizes, we model the problem as unrelated parallel batch machines problem with incompatible job families and unequal ready times of the jobs. Our objective is to minimize the total weighted tardiness (TWT) of the jobs. Given that the problem is NP-hard, we propose two different solution approaches. The first approach works with a time window-based mixed integer programming (MIP) decomposition. The second approach uses a variable neighbourhood search (VNS). Using randomly generated test instances, we show that the proposed algorithms outperform common dispatching rules that cannot deal with the given constraints effectively.

Are Simulation Standards in Our Future?
Hans Ehm (Infineon), Leon McGinnis (Georgia Institute of Technology) and Oliver Rose (Dresden University of Technology)

Abstract:
This panel seeks to initiate a discussion within the manufacturing simulation community about a fundamental change in the way we think about, teach, and implement manufacturing simulation. Today, manufacturing simulation, while based on formal simulation languages, is largely an artistic process. We teach manufacturing simulation as a studio course, i.e., students learn an esthetic for manufacturing simulation, learn by example, and their progress is evaluated through studies in which they create simulations. We are not surprised, in fact fully expect that two simulationists will create possibly quite different simulation of the same situation, even using the same language.

A Simple Example of SysML Driven Simulation
Leon McGinnis and Volkan Ustun (Georgia Institute of Technology)

Abstract:
The successful practice of simulation requires a number of capabilities; two key capabilities are creating a conceptual model of the system to be simulated, and translating the conceptual model to a computational process or simulation program. We describe how OMG’s new graphical systems modeling language, OMG SysML™ (OMG 2009), can be used to create a conceptual model, and how this conceptual model can be translated automatically to a simulation program. In demonstrating the process, we use Arena™ as the target simulation language, but the concepts presented are quite general.

First Steps Towards a General SysML Model for Discrete Processes in Production Systems
Oliver Schönherr and Oliver Rose (Dresden University of Technology)

Abstract:
In many areas of science, like computer science or electrical engineering, modeling languages have been established, however, this is not the case in the field of discrete processes. There are two reasons which motivate such a development: 1. Modeling languages allow realizing projects by the principles of systems engineering. So one obtains clearness even for large projects and reduces the discrepancy between model and reality. 2. Modeling languages are a central part of automatic code generation. In this paper, we present our first steps in developing a simulation-tool-independent description of production systems and first ideas on how to convert such a general model into simulation-tool-specific models.

A Method for Cycle Time Estimation of Semiconductor Manufacturing Toolsets with Correlations
Raha Akhavan-Tabatabaei (North Carolina State University) and Shengwei Ding and George Shanthikumar (UC Berkeley)

Abstract:
This paper proposes a cycle time estimation method for typical toolsets in Semiconductor Fabrication Facilities (Fabs). Due to sophisticated process flows and requirements of the process, queueing models for toolsets can become very complicated and their performance has been unsatisfactory due to the low accuracy of their results. In this paper, we first study the performance of classical queuing models using a high volume manufacturing toolset as our case study and discuss the potential causes for failure of classical models in predicting its cycle time. Then we propose a new approach for estimating the cycle time of toolsets that have inherent correlation between their arrival and service processes. Finally we apply this method to our case study toolset and show that the accuracy of cycle time estimation is improved significantly compared to use of classical queueing models.

Optimizing Demand Fulfillment From Test Bins
Brittany M. Bogle and Scott J. Mason (University of Arkansas)

Abstract:
A primary component of the wafer assembly and final testing phases of the semiconductor manufacturing process is the process of binning wherein integrated circuits are tested for speed, voltage, and other functionality requirements. Customer demand for products is satisfied using binned components. While higher functionality components can be used to satisfy lower-level demand at a profit loss, the reverse case is not an option. We investigate the important question of satisfy customer demand from available binned devices with maximum profit in terms of maximizing revenue and minimizing inventory holding costs using a mathematical programming-based solution approach. Initial results suggest our model is able to accurately produce cost-effective demand fulfilment strategies for semiconductor manufacturers in practice.